Unit 5: Serial Communication & Industrial Interfaces - Practice Quiz

1 What does UART stand for?

2 Which two signal lines are commonly used for basic UART communication?

3 What must two UART devices normally share for successful communication?

4 Which two lines are used by the I2C protocol?

5 How does an I2C controller normally select a particular target device?

6 What is the main purpose of pull-up resistors on I2C lines?

7 Which SPI signal carries data from the controller to a peripheral?

8 Which SPI line is used to select a specific peripheral?

9 Which statement describes a common feature of SPI?

10 What is the purpose of bus arbitration?

11 What is the main purpose of an address on a shared communication bus?

12 What does a protocol analyzer primarily help a developer inspect?

13 Which tool is commonly used to capture multiple digital communication lines over time?

14 What type of standard is RS485 primarily?

15 Which communication method is used by RS485 to improve noise resistance?

16 What is Modbus commonly used for?

17 What is a key benefit of using an I2C interface with an LCD module?

18 Which characteristic is commonly associated with OLED displays?

19 What is the main purpose of a data logging system?

20 Which factor is especially important when logging rapidly changing sensor data?

21 A UART link uses 8 data bits, no parity, and 1 stop bit. At 115200 baud, what is the maximum theoretical payload rate?

22 A UART receiver repeatedly reports framing errors even though the TX and RX wires are connected correctly. Which configuration mismatch is the most likely cause?

23 Two UART devices are configured for 9600 baud, 8 data bits, even parity, and 1 stop bit. How many bits are transmitted for each data byte?

24 An I2C bus works at 100 kHz but becomes unreliable after several modules are added. The observed SDA and SCL rising edges are too slow. What is the most appropriate correction?

25 An I2C scanner reports address 0x3C. A device data sheet describes its address byte as 0x78 for writing. Why do the values differ?

26 An I2C master writes a register address and then needs to read data from the same slave without releasing the bus. Which bus event should it generate?

27 An SPI sensor changes its output data on the falling clock edge and expects the controller to sample it on the rising edge. The clock is idle low. Which SPI mode should be selected?

28 A controller connects to three standard SPI sensors that share SCLK, MOSI, and MISO. How should the controller normally select one sensor for communication?

29 An SPI ADC sends one 16-bit sample during each transaction. With a 4 MHz SPI clock and no transaction overhead, how long does one sample transfer take?

30 Two I2C masters begin transmitting simultaneously. One sends a 1 while the other sends a 0 at the same bit position. What happens to the master that sends the 1?

31 Two I2C temperature sensors have the same fixed 7-bit address and must operate on one controller. Which solution is most appropriate when their addresses cannot be changed?

32 A logic analyzer decodes an SPI transaction into incorrect byte values, but the captured clock and data waveforms look stable. What should be checked first?

33 An I2C protocol analyzer shows the address followed by a NACK on every transaction. The electrical levels and clock frequency are valid. Which issue should be investigated next?

34 A UART capture appears as unreadable bytes in a protocol analyzer, but the measured bit period is approximately 104 microseconds. Which decoder baud rate should be tried?

35 An RS485 Modbus RTU network is unstable only when a long cable is installed. Where should termination resistors normally be placed?

36 A Modbus RTU master needs to read a block of holding registers from a slave. Which standard function code should it use?

37 A two-wire RS485 transceiver receives its own transmitted data correctly but no remote reply is detected. Which control error is most likely?

38 An I2C character LCD acknowledges commands, but only dark blocks appear on the first row. What should be checked first?

39 A monochrome OLED has a resolution of 128 by 64 pixels and stores one bit per pixel. How much memory is required for a full frame buffer?

40 A logger samples four 16-bit channels at 20 kHz per channel. Ignoring headers and timestamps, what minimum sustained storage write rate is required?

41 A UART uses a 48 MHz peripheral clock, 16-times oversampling, and an integer baud-rate divisor , where . Which divisor gives the smallest error for a target of 115200 baud?

42 A UART link operates at 115200 baud using 8 data bits, even parity, one start bit, and one stop bit. Assuming continuous transmission with no gaps, what is the maximum application-data throughput?

43 A UART receives at 921600 baud in 8N1 format using circular DMA. Software may take up to 3 ms between buffer checks. Ignoring interrupt latency, what is the minimum usable DMA-buffer capacity that prevents overwrite during one such interval?

44 A 3.3 V Fast-mode I2C bus has 200 pF capacitance. The rise-time limit is 300 ns, with . Devices can sink 3 mA while keeping V. Which pull-up range satisfies both constraints?

45 To read from a 10-bit-addressed I2C target after selecting an internal register, which address-phase sequence is required without issuing a STOP?

46 During an I2C read, a protocol trace shows SCL held low for 600 microseconds immediately after the target ACKs the register address, while SDA remains stable. What is the most appropriate controller behavior?

47 An SPI peripheral specifies that SCLK idles high, data changes on falling edges, and data is sampled on rising edges. Which SPI mode matches this timing?

48 Three 12-bit SPI output devices are daisy-chained as MCU to A to B to C. A common latch signal updates all devices after shifting. To load words , , and into A, B, and C respectively, what sequence is required?

49 Two I2C controllers begin simultaneously and transmit identical address and data bits until one sends a logic 1 while the other sends a logic 0. What happens at that bit?

50 A datasheet lists an I2C device's write address as 0xA0 and read address as 0xA1. What 7-bit address should be passed to an API that accepts the address separately from the read/write direction?

51 A logic analyzer decodes an I2C NACK, but the controller reports that an ACK was received. An oscilloscope shows SDA rising slowly and crossing the analyzer threshold before crossing the controller's guaranteed input-high threshold. What is the most likely cause?

52 Rare RS485 frame failures occur only when a nearby motor starts. A digital analyzer shows syntactically valid bytes but occasional CRC errors. Which measurement is most useful for identifying the physical-layer cause?

53 A Modbus RTU link runs at 9600 baud with 11 transmitted bits per character. Using the 3.5-character frame-separation rule, what minimum silent interval is required?

54 A Modbus RTU implementation computes a CRC value of 0x4B37 for a frame. In what order must the CRC bytes be transmitted?

55 A half-duplex RS485 Modbus network uses a single linear cable with several short device stubs. Which termination and bias arrangement is generally correct?

56 A character LCD is connected through a PCF8574-style quasi-bidirectional I2C expander. Why must firmware write logic 1 to the expander pin connected to LCD D7 before reading the LCD busy flag?

57 A 128 by 64 monochrome OLED uses a 1024-byte framebuffer over 400 kHz I2C. One address byte and one control byte are sent per frame, and every transmitted byte requires 9 clock pulses including ACK. Ignoring START and STOP timing, what is the maximum full-frame update rate?

58 A logger samples eight 16-bit channels at 50 ksample/s per channel. Its storage device can stall for 120 ms. What minimum usable buffering is required solely to absorb data produced during the stall?

59 A data source produces 4 MB/s continuously. Storage writes at 20 MB/s when active but may pause for 200 ms once every 5 seconds. Assuming no other overhead, which buffer size is the minimum needed to survive one pause while remaining sustainable afterward?

60 A logger timestamps records with a 32-bit unsigned microsecond counter. Which method correctly handles a single counter wrap when computing the interval between consecutive records?