Unit 5: Serial Communication & Industrial Interfaces

I. Foundations of Serial Communication

Serial communication transfers data sequentially over one or more signal lines, enabling microcontrollers, sensors, displays, computers, and industrial controllers to exchange information. Unlike parallel communication, it reduces wiring and pin count, but requires agreed timing, framing, electrical levels, and error-handling rules.

• Defining properties:
  • Bit sequence: Data is transmitted one bit at a time, usually with the most significant bit (MSB) or least significant bit (LSB) sent first.
  • Duplex mode: A link may be simplex, half-duplex, or full-duplex.
  • Synchronization: UART is asynchronous; I2C and SPI use explicit clock signals.
  • Topology: Links may be point-to-point, multi-drop, or multi-controller buses.
  • Electrical interface: Logic protocols such as UART differ from physical standards such as TTL, RS-232, and RS485.
  • Performance measures: Baud rate, bit rate, latency, throughput, clock frequency, and error rate determine link performance.
  • Data integrity: Parity, checksums, cyclic redundancy checks (CRCs), acknowledgements, and retries detect or recover from errors.
  • Common reference: Unless differential signaling is used, communicating devices normally require a shared ground.

II. UART — Asynchronous Point-to-Point Communication

A. UART serial communication protocol

Universal Asynchronous Receiver/Transmitter (UART) communication sends framed characters without a shared clock, so both endpoints must use compatible timing and frame settings.

• Signal lines:
  • TX: Transmits serial data.
  • RX: Receives serial data.
  • GND: Establishes the common voltage reference.
  • Full-duplex communication uses TX and RX simultaneously; TX of one device connects to RX of the other.
• Idle and framing: The line normally remains logic high, begins with a low start bit, carries data bits, and ends with one or more high stop bits.
• Typical format: 9600 8N1 means 9600 baud, 8 data bits, no parity, and 1 stop bit.
• Bit order: Standard UART commonly sends the least significant data bit first.
• Character time:

Tframe = Nbits / B

• Tframe = time per frame in seconds.
• Nbits = total start, data, parity, and stop bits.
• B = baud rate in symbols per second.

• Worked example: At 9600 baud using 8N1, each byte occupies 10 bits, so Tframe = 10/9600 ≈ 1.04 ms; ideal payload throughput is about 960 bytes/s.
• Parity: Even or odd parity detects some single-bit errors but cannot correct them.
• Limitations: Clock mismatch, noise, incorrect voltage levels, or mismatched frame settings produce framing errors and corrupted characters. A 3.3 V UART must not be connected directly to incompatible RS-232 voltage levels.

III. I2C — Addressed Two-Wire Bus

A. I2C serial communication protocol

Inter-Integrated Circuit (I2C) is a synchronous, address-based bus that connects multiple controller and target devices using only two open-drain signal lines.

• Bus lines:
  • SDA: Bidirectional serial data.
  • SCL: Serial clock, usually generated by the active controller.
• Pull-up resistors: SDA and SCL cannot actively drive high; external resistors pull them toward the supply, commonly 3.3 V or 5 V.
• Transaction sequence:
  1. A START condition occurs when SDA falls while SCL is high.
  2. The controller sends a 7-bit address and read/write bit.
  3. The addressed target responds with ACK by pulling SDA low on the ninth clock.
  4. Data bytes and ACK/NACK bits follow.
  5. A STOP occurs when SDA rises while SCL is high.
• Addressing: Seven-bit addressing is common, giving address values from 0x00 to 0x7F, although some are reserved. Ten-bit addressing expands the address space.
• Clock rates: Common modes include Standard-mode at 100 kbit/s, Fast-mode at 400 kbit/s, and Fast-mode Plus at 1 Mbit/s.
• Clock stretching: A target may hold SCL low to delay the controller while completing an operation.
• Advantages: Multiple addressed peripherals share two microcontroller pins.
• Limitations: Pull-up resistance and bus capacitance limit rise time, speed, and practical cable length; I2C is primarily intended for short board-level connections.

IV. SPI — High-Speed Synchronous Communication

A. SPI serial communication protocol

Serial Peripheral Interface (SPI) is a synchronous controller-peripheral protocol optimized for high speed and simple full-duplex transfers.

• Core signals:
  • SCLK: Clock from the controller.
  • MOSI: Controller-out, peripheral-in data.
  • MISO: Controller-in, peripheral-out data.
  • CS/SS: Chip-select line that activates a peripheral, commonly at logic low.
• Transfer principle: Controller and peripheral shift one bit per clock edge; sending and receiving can occur simultaneously.
• SPI modes: Clock polarity (CPOL) selects the idle clock level, while clock phase (CPHA) selects the sampling edge. Their combinations define modes 0–3.
• Selection method: Multiple peripherals can share SCLK, MOSI, and MISO, but normally require separate chip-select signals.
• Throughput:

Raw bit rate ≈ fSCLK
Transfer time = Number of bits / fSCLK

• fSCLK = serial clock frequency in hertz.

• Advantages: SPI has low protocol overhead, deterministic timing, and clock rates often reaching several megahertz.
• Limitations: It has no standard device addressing, acknowledgement, or built-in error detection. Additional peripherals increase chip-select wiring, and incompatible SPI modes cause shifted or invalid data.

V. Shared-Bus Coordination

A. Bus arbitration and addressing

Bus arbitration determines which controller may use a shared bus, while addressing determines which target must respond.

• I2C arbitration: Multiple controllers monitor SDA while transmitting. Because a low level dominates a released high level, a controller sending high but observing low loses arbitration and stops transmitting.
• Non-destructive result: The winning I2C message continues without corruption; arbitration commonly resolves differences in address or data bits.
• Address conflicts: Two targets with the same I2C address respond together, causing incorrect data or contention.
• Conflict solutions:
  • Change configurable address pins.
  • Use an I2C multiplexer such as the TCA9548A.
  • Place devices on separate buses.
• SPI addressing: Chip-select lines provide physical selection rather than an address field.
• UART addressing: Basic UART has no addressing; multi-drop systems add addresses in a higher-level protocol such as Modbus.
• Design requirement: Firmware should define ownership, transaction timeouts, and recovery procedures for a bus stuck low or held indefinitely.

VI. Communication Diagnosis

A. Protocol analyzers and debugging

Protocol analyzers capture electrical activity and decode communication frames, allowing faults to be connected to exact bits, timing events, and protocol fields.

• Oscilloscope: Displays analog voltage, ringing, noise, rise time, and overshoot; it is essential when logic levels appear valid digitally but signal integrity is poor.
• Logic analyzer: Samples multiple digital channels and decodes UART, I2C, or SPI transactions.
• UART checks: Confirm baud rate, data bits, parity, stop bits, idle polarity, crossed TX/RX lines, and common ground.
• I2C checks: Inspect START/STOP conditions, address bytes, ACK/NACK responses, clock stretching, and slow pull-up edges.
• SPI checks: Verify chip-select timing, CPOL, CPHA, bit order, word length, and whether MISO becomes high-impedance when deselected.
• Triggering: Useful triggers include an I2C address, UART byte, SPI chip-select edge, or error event.
• Systematic method:
  1. Verify supply voltage and ground.
  2. Measure idle signal levels.
  3. Capture one minimal transaction.
  4. Compare waveform timing with configuration.
  5. Add checksum, sequence number, or diagnostic logging to isolate intermittent faults.
• Sampling rule: A digital analyzer should sample several times faster than the signal frequency; higher sampling provides more reliable edge placement.

VII. Industrial Multi-Drop Communication

A. Interfacing industrial modules using Modbus and RS485

Industrial modules commonly combine the RS485 differential physical layer with Modbus RTU messaging to communicate reliably over long, noisy, multi-drop networks.

• RS485 signaling: Data is represented by the voltage difference between lines A and B, improving common-mode noise rejection compared with single-ended signaling.
• Topology: A daisy-chain bus is preferred; long star branches and stubs create reflections.
• Half-duplex control: Two-wire transceivers use driver-enable pins such as DE and receiver-enable pins such as /RE; firmware enables transmission only while sending.
• Termination: A resistor commonly near 120 Ω is placed at each physical end of a long bus to match cable impedance.
• Biasing: Fail-safe bias resistors establish a known idle state when no transmitter is active.
• Modbus RTU frame:

[Device address][Function code][Data][CRC-16]

• Fields: The address selects a server, the function code identifies an operation such as reading holding registers, and CRC-16 detects frame corruption.
• Timing: Modbus RTU separates frames with a silent interval of at least 3.5 character times.
• Register interpretation: Devices may differ in register numbering, byte order, word order, scaling, and signed representation; these must match the module documentation.
• Reliability: Use timeouts, bounded retries, unique addresses, shielded twisted-pair cable, and one active client/controller on a conventional Modbus RTU bus.

VIII. Display Interfaces

A. I2C LCD and OLED display interfacing

I2C display modules reduce pin usage by accepting addressed commands and display data over SDA and SCL.

• I2C LCD: A character LCD such as a 16×2 HD44780 module often uses a PCF8574 I/O expander backpack. The expander converts I2C bytes into LCD control and four-bit data signals.
• OLED module: Small displays commonly use an SSD1306 controller with resolutions such as 128×64 pixels.
• Initialization: Firmware configures the I2C address, display geometry, operating mode, contrast, and screen state before writing content.
• Address discovery: An I2C scanner can identify responding addresses; common modules often provide solder jumpers for address selection.
• Text versus graphics:
  1. Character LCDs store predefined character patterns and require little memory.
  2. OLEDs support pixel graphics but may require a framebuffer; a 128×64 monochrome image needs 128 × 64 / 8 = 1024 bytes.
• Practical concerns: Confirm voltage compatibility, pull-up placement, address format, refresh rate, and library/controller match.
• Performance: Updating only changed characters or screen regions reduces I2C traffic and visible flicker.

IX. Continuous Data Acquisition

A. High-speed data logging systems

High-speed data logging acquires, timestamps, buffers, and stores data without losing samples when sensors produce data faster than storage can respond continuously.

• Throughput requirement:

R = fs × N × b / 8

• R = payload rate in bytes/s.
• fs = samples per second per channel.
• N = number of channels.
• b = bits stored per sample.

• Worked example: Four channels sampled at 10 ksample/s with 16-bit storage require 10,000 × 4 × 16 / 8 = 80,000 bytes/s, excluding timestamps and headers.
• Acquisition path: Sensor or ADC data moves through SPI, DMA, RAM buffers, and then to SD card, flash memory, or a network interface.
• Double buffering: While DMA fills one buffer, firmware writes the other, separating real-time acquisition from variable storage latency.
• Storage strategy: Binary records provide higher throughput than formatted text because decimal conversion and separators add processing and bytes.
• Timing: Hardware timers provide uniform sampling; RTCs or synchronized clocks provide absolute timestamps.
• Integrity controls: Sequence numbers reveal dropped blocks, CRCs detect corruption, and metadata records sample rate, channel identity, units, and calibration.
• Bottlenecks: SD-card erase pauses, filesystem overhead, bus contention, insufficient RAM, and blocking firmware can cause data loss.
• Robust design: Pre-allocate files, write large aligned blocks, monitor buffer occupancy, record overflow events, and stop acquisition safely before removing power.