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Unit 4: Input-Output Organization - Practice Quiz

CSE211 — Computer Organization And Design 60 Questions
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1 Which of the following is an example of an input peripheral device?

Peripheral Devices Easy
A. Printer
B. Monitor
C. Keyboard
D. Speaker

2 Peripheral devices are also commonly referred to as:

Peripheral Devices Easy
A. I/O devices
B. Cache units
C. Control units
D. Arithmetic units

3 Which peripheral is classified as both an input and output device?

Peripheral Devices Easy
A. Plotter
B. Touch screen
C. Scanner
D. Mouse

4 The main purpose of an I/O interface is to:

Input Output Interface Easy
A. Increase the CPU clock speed
B. Perform arithmetic operations
C. Store the operating system
D. Resolve differences between CPU and peripherals

5 In isolated I/O, the memory and I/O addresses are:

Input Output Interface Easy
A. Always shared
B. Merged into one
C. Kept separate
D. Never used

6 When memory and I/O devices share the same address space, the technique is called:

Input Output Interface Easy
A. Isolated I/O
B. Buffered I/O
C. Direct I/O
D. Memory-mapped I/O

7 A priority interrupt system is used to:

Priority interrupt Easy
A. Decide which interrupt is serviced first
B. Reduce clock frequency
C. Store interrupt data permanently
D. Increase memory size

8 In a daisy-chaining priority scheme, devices are connected in:

Priority interrupt Easy
A. Serial order
B. Parallel only
C. A star topology
D. A random order

9 A software method of establishing interrupt priority is called:

Priority interrupt Easy
A. Buffering
B. Caching
C. Pipelining
D. Polling

10 DMA allows data transfer between memory and I/O devices:

Direct memory access transfer Easy
A. Only during interrupts
B. Only through the CPU
C. Using only registers
D. Without CPU intervention

11 During a DMA transfer, the CPU relinquishes control of the:

Direct memory access transfer Easy
A. Program counter
B. Instruction register
C. Stack pointer
D. System buses

12 The signal a DMA controller sends to request bus control from the CPU is the:

Direct memory access transfer Easy
A. Reset signal
B. Clock signal
C. Bus request signal
D. Refresh signal

13 Transferring a whole block of data at once via DMA is called:

Direct memory access transfer Easy
A. Burst transfer
B. Serial transfer
C. Cycle stealing
D. Handshake transfer

14 Which mode of data transfer keeps the CPU continuously checking a status flag?

Modes of data transfer Easy
A. DMA transfer
B. Programmed I/O
C. Interrupt-driven I/O
D. IOP transfer

15 In interrupt-initiated I/O, the device informs the CPU by:

Modes of data transfer Easy
A. Resetting the system
B. Polling the CPU
C. Sending an interrupt signal
D. Halting the memory

16 Which data transfer mode is fastest for large amounts of data?

Modes of data transfer Easy
A. Manual transfer
B. Programmed I/O
C. DMA transfer
D. Polling

17 UART stands for:

UART Easy
A. Unified Access Register Table
B. United Address Return Track
C. Universal Asynchronous Receiver Transmitter
D. Universal Analog Read Timer

18 A UART primarily converts data between:

UART Easy
A. Binary and decimal forms
B. Analog and digital forms
C. ASCII and Unicode forms
D. Serial and parallel forms

19 In asynchronous serial transmission, each character frame typically begins with a:

UART Easy
A. Parity bit
B. Data bit
C. Stop bit
D. Start bit

20 An Input/Output Processor (IOP) is best described as a:

Input/Output Processor Easy
A. Processor dedicated to handling I/O operations
B. Type of main memory
C. Cache controller
D. Power supply unit

21 A device transfers data to the CPU at a rate that the CPU cannot control, and data must be read exactly when it arrives. Which category of peripheral behaviour does this best describe?

Peripheral Devices Medium
A. A programmed polling device
B. A memory-mapped output device
C. An interrupt-driven storage device
D. A synchronous input device

22 Why do most peripheral devices require an interface circuit rather than connecting directly to the CPU bus?

Peripheral Devices Medium
A. To convert virtual addresses into physical addresses
B. To reduce the number of memory locations used by programs
C. To increase the clock frequency of the CPU
D. To resolve differences in data rate, signal level, and format between device and CPU

23 In isolated (I/O-mapped) I/O, how does the CPU distinguish an access to an I/O port from an access to memory?

Input Output Interface Medium
A. By using the same instructions but a different data bus
B. By using separate control lines and dedicated I/O instructions
C. By disabling interrupts during I/O operations
D. By checking the most significant address bit

24 A system uses memory-mapped I/O. What is a direct consequence of this design choice?

Input Output Interface Medium
A. Part of the memory address space is consumed by I/O ports
B. Separate IN and OUT instructions become mandatory
C. The CPU requires an additional dedicated I/O bus
D. I/O devices can no longer generate interrupts

25 In a daisy-chain priority interrupt scheme, how is priority among devices determined?

Priority interrupt Medium
A. By a programmable priority register in each device
B. By the physical position of the device in the chain
C. By the interrupt vector number assigned to the device
D. By the order interrupts are received in time

26 A priority encoder for 4 interrupt sources produces which of the following outputs?

Priority interrupt Medium
A. A 4-bit one-hot code for all active requests
B. A 4-bit mask disabling lower-priority requests
C. A 2-bit code identifying the highest-priority active request
D. A single bit indicating any interrupt is active

27 In a priority interrupt system, what is the primary purpose of the interrupt mask register?

Priority interrupt Medium
A. To count the number of pending interrupts
B. To store the return address during an interrupt
C. To hold the vector address of the current interrupt
D. To selectively enable or disable individual interrupt sources

28 During a DMA transfer in cycle-stealing mode, what happens to the CPU?

Direct memory access transfer Medium
A. It switches to executing the DMA controller's microcode
B. It is paused only for the individual bus cycles the DMA uses
C. It is halted for the entire duration of the block transfer
D. It continues executing without ever releasing the bus

29 A DMA controller is configured with a starting address of 2000 and a word count of 512. After transferring 200 words, what values do the address register and count register hold (word-addressed)?

Direct memory access transfer Medium
A. Address 2200 and count 312
B. Address 1800 and count 312
C. Address 2512 and count 200
D. Address 2000 and count 512

30 Why must the CPU issue a bus grant (BG) signal before a DMA controller can begin a transfer?

Direct memory access transfer Medium
A. To load the starting address into the DMA controller
B. To generate an interrupt at the end of the transfer
C. To reset the DMA word-count register to zero
D. To relinquish control of the address, data, and control buses to the DMA

31 In programmed I/O, what does the CPU spend most of its time doing while waiting for a slow device?

Modes of data transfer Medium
A. Repeatedly reading and testing the device status flag
B. Servicing interrupts from the device
C. Executing other user programs in the background
D. Transferring data directly to memory via DMA

32 Which mode of data transfer allows the CPU to continue useful work and be notified only when a device needs service?

Modes of data transfer Medium
A. Synchronous polling I/O
B. Interrupt-initiated I/O
C. Programmed I/O
D. Handshaking I/O

33 For transferring a large block of data from a high-speed disk to memory with minimal CPU involvement, which mode is most appropriate?

Modes of data transfer Medium
A. Direct memory access (DMA)
B. Handshaking with strobe control
C. Programmed I/O with polling
D. Interrupt-driven single-word transfer

34 In the strobe control method of asynchronous data transfer, what is a key limitation compared to handshaking?

Modes of data transfer Medium
A. It requires two control lines instead of one
B. The sender cannot confirm the receiver actually accepted the data
C. It needs a shared clock between devices
D. It works only for output operations

35 A UART is configured for 8 data bits, 1 start bit, 1 stop bit, and no parity. What fraction of each transmitted frame carries actual data?

UART Medium
A.
B.
C.
D.

36 In a UART, what is the primary function of the shift registers used during transmission and reception?

UART Medium
A. Detecting parity errors in received frames
B. Generating the baud-rate clock signal
C. Converting between parallel CPU data and serial line data
D. Storing multiple frames for buffered transfer

37 A UART transmits data asynchronously. How does the receiver know when a new character begins?

UART Medium
A. By detecting the falling edge of the start bit
B. By checking the parity bit value first
C. By counting a fixed idle interval between characters
D. By reading a shared synchronizing clock line

38 How does an Input/Output Processor (IOP) differ fundamentally from a simple DMA controller?

Input/Output Processor Medium
A. An IOP cannot access main memory directly
B. An IOP can execute its own I/O program with instructions, not just transfer data
C. An IOP transfers only one word at a time to memory
D. An IOP requires the CPU to remain halted during transfers

39 In an IOP-based system, how do the CPU and IOP typically coordinate their activities?

Input/Output Processor Medium
A. By sharing the same instruction register during execution
B. By running from a single common program counter
C. By the CPU directly controlling every I/O device register
D. Through commands and status information exchanged in shared memory

40 What is the main advantage of using an IOP in a computer system with heavy I/O demands?

Input/Output Processor Medium
A. Main memory size requirements are reduced significantly
B. The CPU is offloaded from managing detailed I/O operations
C. Interrupts are eliminated entirely from the system
D. Peripheral devices become synchronous with the CPU clock

41 A DMA controller transfers data in cycle-stealing mode. The CPU has a memory cycle time of , and the I/O device produces data at (one byte per transfer). What fraction of the memory bandwidth is consumed by DMA?

Direct memory access transfer Hard
A.
B.
C.
D.

42 In a daisy-chain priority scheme with 4 devices, the priority-in () of the highest device is tied to 1. If device 2 (second in chain) is requesting an interrupt while device 1 is not, what are the (priority-out) values of devices 1, 2, 3, and 4 respectively?

Priority interrupt Hard
A.
B.
C.
D.

43 A UART is configured for baud, 8 data bits, even parity, and 2 stop bits. What is the effective data throughput in bytes per second (payload only)?

UART Hard
A.
B.
C.
D.

44 In programmed I/O, the CPU wastes cycles polling a status flag. If checking the flag takes and a device becomes ready on average every , roughly how many polling checks are wasted per transfer?

Modes of data transfer Hard
A.
B.
C.
D.

45 An isolated I/O (I/O-mapped) system uses separate control lines for memory and I/O. Which is the primary architectural disadvantage compared to memory-mapped I/O?

Input Output Interface Hard
A. It forces all I/O to use DMA exclusively
B. Only specialized I/O instructions (IN/OUT) can access ports, limiting addressing/manipulation flexibility
C. It cannot support interrupt-driven transfers
D. It requires more address lines than memory-mapped I/O for the same port count

46 A DMA controller has a 16-bit address register and a 16-bit word-count register. It starts at address with a count of . After transferring in burst mode, at what address does the last word get written, assuming byte-addressable memory and 1 byte per transfer?

Direct memory access transfer Hard
A.
B.
C.
D.

47 A parallel priority interrupt system uses a mask register and a priority encoder. If the mask register is (bit position 0 is highest priority, MSB) and pending interrupts are , which interrupt (bit position) will be serviced?

Priority interrupt Hard
A. Bit position 0 (highest)
B. Bit position 3 (lowest)
C. Bit position 2
D. Bit position 1

48 In an IOP-based system, the CPU issues a command to the IOP by placing an instruction in memory and executing a specific operation. What is the term for the CPU-to-IOP communication that initiates channel program execution?

Input/Output Processor Hard
A. A direct memory access cycle-steal request
B. A polling loop that busy-waits on the IOP status register
C. An interrupt vector fetch from the IOP
D. Test I/O / Start I/O instruction that hands off a command word to the IOP

49 A UART receiver samples each incoming bit at the baud rate. If the transmitter clock is faster than the receiver clock, after how many bits (from the start bit sampling point) is there risk of sampling the wrong bit, given the sample point drifts by per bit relative to center?

UART Hard
A. Around 100 bits
B. Around 25 bits (drift accumulates to ~half a bit period)
C. Around 8 bits
D. Around 50 bits

50 Consider transferring a block. Interrupt-driven I/O costs overhead per byte (context save/restore), while DMA costs a fixed setup plus per byte. What is the approximate speedup of DMA over interrupt-driven I/O?

Modes of data transfer Hard
A. About
B. About
C. About
D. About

51 A hard disk rotates at with an average seek time of and a transfer rate of . What is the approximate average access time to read a block?

Peripheral Devices Hard
A. About
B. About
C. About
D. About

52 During DMA, the CPU is temporarily disconnected from the buses. Which technique allows the CPU to continue executing from cache/registers while DMA proceeds, minimizing stalling?

Direct memory access transfer Hard
A. Disabling all interrupts during DMA
B. Cycle stealing combined with CPU operating from cache when no memory access is needed
C. Using memory-mapped I/O instead of isolated I/O
D. Forcing all DMA into burst mode

53 In a system with an interrupt priority structure, a low-priority ISR is executing when a higher-priority interrupt arrives. For correct nested handling, what must the low-priority ISR have done immediately upon entry?

Priority interrupt Hard
A. Disabled all interrupts permanently until it completes
B. Cleared the mask register to zero
C. Saved state and re-enabled interrupts (with priority masking) to permit higher-priority preemption
D. Signaled priority-out as 1 to all lower devices

54 An I/O interface uses a status register with a busy flag and a done flag. A subtle race occurs if the CPU reads data before checking done. Which handshaking property prevents this data-corruption edge case?

Input Output Interface Hard
A. The interface uses tri-state buffers on the data bus
B. The interface asserts done only after the data buffer is fully latched and stable
C. The done flag is cleared automatically on power-up
D. The CPU polls the busy flag twice for confirmation

55 A selector channel and a multiplexer channel differ fundamentally. Which statement correctly characterizes a multiplexer (byte-multiplexer) channel?

Input/Output Processor Hard
A. It dedicates the full channel to one high-speed device until the transfer completes
B. It interleaves bytes from multiple slow devices, servicing them concurrently in a time-shared manner
C. It can only be used with memory-mapped I/O
D. It requires no subchannel status storage

56 A processor runs at . Handling one interrupt costs cycles of overhead. A device interrupts times per second. What percentage of CPU time is spent on interrupt overhead alone?

Modes of data transfer Hard
A.
B.
C.
D.

57 A UART's transmit shift register and transmit holding register are separate. Why does this double buffering improve throughput at high baud rates?

UART Hard
A. The CPU can load the next byte into the holding register while the current byte is still shifting out, eliminating inter-byte gaps
B. It removes the need for start and stop bits
C. It allows parity to be computed twice for reliability
D. It doubles the effective baud rate of the line

58 Comparing an SSD and an HDD for random 4 KB reads, the SSD dominates. Which architectural property of the SSD is the primary reason?

Peripheral Devices Hard
A. Higher sequential transfer bandwidth alone
B. Larger onboard DRAM cache exclusively
C. Absence of mechanical seek and rotational latency, giving near-constant low access latency
D. Use of DMA instead of programmed I/O

59 In a system with cache, DMA writing to main memory can cause a coherence problem. What is the specific hazard if the CPU later reads that memory region?

Direct memory access transfer Hard
A. The DMA controller overwrites the cache directly, corrupting tags
B. The CPU cannot access memory during DMA at all
C. The CPU may read stale cached data instead of the newer DMA-written data unless the cache line is invalidated
D. The DMA transfer count register underflows

60 A vectored interrupt system stores the ISR address in a vector table. Compared to polled interrupts, what is the key latency advantage, and its main cost?

Priority interrupt Hard
A. Faster dispatch since the source is identified directly by its vector, at the cost of extra hardware for vector generation
B. Lower latency and it eliminates the need for any ISR
C. Identical latency but simpler hardware than polling
D. Faster dispatch but it cannot support priorities
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