Unit 3: Central Processing Unit - Practice Quiz

1 A stack follows which order of data access?

2 The two basic operations performed on a stack are:

3 The register that holds the address of the top element of a stack is called the:

4 Which arithmetic expression notation is naturally suited for stack-based evaluation?

5 In a general register organization, the connections between registers and the ALU are commonly established using:

6 What is the main advantage of using a large number of CPU registers?

7 In immediate addressing mode, the operand is:

8 In register addressing mode, the operand is present in:

9 Which addressing mode uses the address field of the instruction to point to a memory location that contains the address of the operand?

10 The addressing mode in which the operand is implicitly defined by the instruction is called:

11 RISC stands for:

12 Which of the following is a characteristic of a RISC processor?

13 CISC stands for:

14 Which feature is typically associated with CISC architecture?

15 The portion of an instruction that specifies the operation to be performed is called the:

16 An instruction format that uses no address field for operands and relies on a stack is called a:

17 Which data transfer scheme allows I/O devices to transfer data to memory without continuous CPU involvement?

18 The register that holds the address of the next instruction to be executed is the:

19 An interrupt is best described as a:

20 The Processor Status Word (PSW) primarily stores:

21 In a general register organization, a microoperation such as is executed. Which control fields are minimally required to specify this operation in a single control word?

22 A CPU has 8 general-purpose registers. How many bits are required for each of the SELA, SELB, and SELD fields in the control word?

23 In a memory stack where SP points to the top item and the stack grows toward lower addresses, which sequence correctly represents a PUSH operation?

24 The arithmetic expression is written in Reverse Polish Notation (postfix). Which is correct?

25 An instruction uses register indirect addressing. If register R contains 4000 and memory location 4000 contains 6000, what is the effective address of the operand?

26 A relative addressing mode instruction has an address field of 500. If the program counter (PC) holds 700 at the time of execution, what is the effective address?

27 Which addressing mode is most suitable for accessing successive elements of an array by incrementing a register between accesses?

28 In indexed addressing mode, the effective address is computed as which of the following?

29 In a typical RISC architecture, which characteristic is a direct consequence of using a load/store design?

30 Overlapped register windows in RISC processors are used primarily to achieve which benefit?

31 Which of the following is a defining feature of a CISC architecture compared to RISC?

32 Why do CISC processors typically rely on microprogrammed control units?

33 A computer has a 32-bit instruction with a 6-bit opcode. If the remaining bits form a single memory address field, what is the maximum directly addressable memory?

34 Evaluating on a zero-address (stack) machine requires which instructions in order?

35 In a three-address instruction format, the statement is typically expressed as which single instruction?

36 In which data transfer scheme does the CPU repeatedly check a status flag to determine if a device is ready, wasting CPU cycles while waiting?

37 During DMA transfer, how does the DMA controller obtain access to the system bus from the CPU?

38 When an interrupt is acknowledged, what must the CPU save before transferring control to the interrupt service routine?

39 In a vectored interrupt system, how is the address of the interrupt service routine determined?

40 After the subtraction is performed in the ALU, which status flag in the processor status word is set?

41 A stack-organized CPU evaluates the postfix expression A B C * + D - using only PUSH and arithmetic operations that pop two operands. If the stack is initially empty, what is the maximum number of elements present on the stack at any point during evaluation?

42 An instruction uses indexed addressing with EA = base + (index register R1). R1 holds , base field is , and memory word at contains , while contains . What value is loaded into the accumulator?

43 A processor has a 32-bit instruction, 64 opcodes, and three register operand fields addressing 32 registers each. How many bits remain for an immediate/displacement field?

44 In a classic RISC pipeline, a load instruction is immediately followed by an instruction that uses the loaded register. Without forwarding, how many stall (bubble) cycles are typically required assuming a 5-stage pipeline where data is available only after the MEM stage?

45 Which characteristic most fundamentally distinguishes a CISC memory-to-memory ADD MEM1, MEM2, MEM3 instruction from a RISC equivalent?

46 A polled interrupt system checks 8 devices in priority order every polling cycle. If the highest-priority device raises frequent requests, which problem is most likely to occur for the lowest-priority device?

47 After computing in an 8-bit signed ALU, which combination of PSW flags is correctly set?

48 In cycle-stealing DMA, a device transfers 2000 words while the CPU runs a program. Each DMA word transfer steals one bus cycle from the CPU. What is the primary effect on the CPU compared to burst-mode DMA?

49 A CPU has a register file with two read ports and one write port feeding an ALU whose output returns to the file. To execute R3 <- R1 + R2 in one clock, what is the minimum requirement on the bus/port structure?

50 A branch instruction at address uses PC-relative addressing with a signed displacement of . The instruction is 4 bytes long and PC is incremented before displacement is added. What is the branch target address?

51 A memory stack grows toward lower addresses with SP pointing to the last item pushed. After executing PUSH then POP once each on an initially empty stack (SP = ), what is the final value of SP, assuming word size of 1?

52 A machine supports zero-, one-, and two-address instructions using expanding opcodes in a 16-bit format with 4-bit register fields. If there are 14 two-address instructions and 31 one-address instructions, how many zero-address instructions can be encoded?

53 During a vectored interrupt, the interrupting device supplies information that the CPU uses to determine the service routine address. What is this supplied information most precisely called?

54 RISC architectures use large register windows with overlapping registers primarily to optimize which operation?

55 Compare programmed I/O and interrupt-driven I/O for a slow device. Which statement is most accurate regarding CPU utilization?

56 A conditional branch BGT (branch if greater than, signed) tests PSW flags. Which flag condition correctly implements signed greater-than after a CMP A, B (A - B)?

57 A microoperation control word for a general register CPU has fields SELA (3 bits), SELB (3 bits), SELD (3 bits), and OPR (5 bits). How many distinct source-register combinations and ALU operations can this word specify (SELA × SELB × OPR)?

58 Which addressing mode is most suitable for implementing position-independent code, where the same program can run correctly regardless of where it is loaded in memory?

59 A CISC processor implements instructions via microprogrammed control. What is the primary trade-off compared to RISC hardwired control?

60 When a maskable interrupt occurs while the interrupt-enable flag is cleared (masked), what is the correct CPU behavior?