Unit 4: Input-Output Organization - Subjective Questions

Peripheral Devices are the input, output, and storage devices connected to a computer system that are external to the CPU and main memory. They allow the computer to communicate with the outside world.

Classification of Peripheral Devices:

• Input Devices: Used to feed data and instructions into the computer.

  • Examples: Keyboard, Mouse, Scanner, Joystick, Light pen, Microphone.

• Output Devices: Used to present processed data (information) to the user.

  • Examples: Monitor, Printer, Plotter, Speakers.

• Input/Output (I/O) Devices: Perform both input and output functions.

  • Examples: Touch screen, Modem, Network cards.

• Storage Devices (Auxiliary/Secondary): Used for permanent storage of data.

  • Examples: Magnetic disk, Magnetic tape, Optical disk (CD/DVD), SSD.

Key Points:

• Peripheral devices operate at speeds much slower than the CPU.
• They use different data formats and word lengths than the CPU.
• An interface is required between peripherals and the CPU to resolve differences in speed, data format, and operating modes.

Need for I/O Interface:

The I/O interface provides a method for transferring information between internal storage (CPU/memory) and external I/O devices. It is required because of several differences between peripherals and the CPU:

• Speed mismatch: Peripherals are electromechanical and slow, while the CPU is electronic and fast.
• Data format difference: Data codes and word lengths in peripherals differ from those in the CPU and memory.
• Operating mode difference: Each peripheral has its own manner of operation which must be controlled independently.
• Signal type difference: Peripheral signals may need conversion to match CPU signals.

Functions of an I/O Interface:

• Data buffering: Temporarily holds data to compensate for speed differences.
• Synchronization: Coordinates timing between the fast CPU and slow peripherals.
• Data format conversion: Converts serial to parallel data and vice versa.
• Command decoding: Interprets commands from the CPU.
• Status reporting: Reports the status of the device (busy, ready, error) to the CPU.
• Error detection: Detects transmission and mechanical errors.
• Address decoding: Recognizes the device address on the bus.

The interface unit typically contains data registers, status registers, control registers, and control logic to perform these functions.

I/O Bus and Interface Modules:

The I/O bus consists of data lines, address lines, and control lines. Each peripheral device has an associated interface unit connected to this bus.

    Data

                Keyboard   Printer    Disk

Communication Process:

1. The CPU places a device address on the address lines.
2. Each interface contains an address decoder that monitors the address lines.
3. When the interface detects its own address, it activates and reads the control lines (function code / command).
4. The function code (I/O command) is interpreted by the interface. Four types of commands:
   • Control command: Activates the peripheral and tells it what to do (e.g., rewind tape).
   • Status command: Tests various status conditions of the device and interface.
   • Data output command: CPU transfers data to the peripheral.
   • Data input command: CPU receives data from the peripheral.

Key Point: Only the interface whose address matches responds; all others ignore the command. This allows a single common bus to serve multiple devices.

Isolated I/O vs Memory-Mapped I/O:

Isolated I/O: The computer has distinct input and output instructions, each associated with an I/O device address. When the CPU fetches and decodes an I/O instruction, it places the address on the address lines and activates an I/O read or write control line.

Memory-Mapped I/O: The CPU treats interface registers as memory locations. There are no specific I/O instructions; the computer uses memory-type instructions to access I/O ports. This gives the programmer flexibility to manipulate I/O data using the complete memory instruction set.

Data transfer between the central computer and I/O devices can be handled in three modes:

1. Programmed I/O:

• Operations are the result of I/O instructions written in the computer program.
• Each data transfer is initiated by an instruction in the program.
• The CPU stays in a program loop (polling/busy-waiting) until the I/O device indicates it is ready.
• Disadvantage: Keeps the CPU busy needlessly, wasting CPU time.
• Suitable for slow, simple systems.

2. Interrupt-Initiated I/O:

• Eliminates the time-wasting polling loop of programmed I/O.
• The interface issues an interrupt request to the CPU when it is ready for transfer.
• The CPU continues executing other tasks; upon receiving the interrupt, it stops the current program, saves context, and services the device via an Interrupt Service Routine (ISR).
• More efficient use of CPU time.

3. Direct Memory Access (DMA):

• The interface transfers data directly to/from memory without CPU involvement.
• A DMA controller takes over the buses to manage the transfer.
• Used for high-speed devices and bulk data transfer (e.g., disk drives).
• The CPU is free during the transfer except for granting bus control.

Summary: Programmed I/O and interrupt I/O involve the CPU in transferring each word, while DMA bypasses the CPU for the actual data movement.

Programmed I/O:

In programmed I/O, data transfer is controlled entirely by program instructions executed by the CPU. Each transfer involves the CPU monitoring the interface until the device is ready.

Process (Flowchart logic):

Transfer to memory
|
More data? --- Yes ---> (loop)
| No
Continue

1. The device places data in its data register and sets a flag (status) bit.
2. The CPU reads the status register repeatedly and checks the flag.
3. If the flag is not set, the CPU loops (busy-wait).
4. When the flag is set, the CPU reads the data from the interface data register and stores it in memory.
5. The process repeats for each word of data.

Advantages:

• Simple to implement.
• Requires little hardware.

Disadvantages:

• The CPU wastes time in the polling loop checking the flag.
• Inefficient when the device is much slower than the CPU.
• Not suitable for high-speed or multiple-device systems.

Interrupt:
An interrupt is a signal sent to the CPU by an I/O device (or other source) requesting attention. It causes the CPU to suspend its current program temporarily and transfer control to an Interrupt Service Routine (ISR).

Interrupt-Initiated I/O:

• Instead of continuously polling the device, the CPU executes other programs.
• When the I/O device is ready, its interface sends an interrupt request to the CPU.
• Upon receiving the interrupt, the CPU:
  1. Completes the current instruction.
  2. Saves the current program counter (PC) and processor status (context).
  3. Branches to the ISR to service the device.
  4. After servicing, restores the saved context and resumes the interrupted program.

How it improves on Programmed I/O:

• Eliminates busy-waiting: The CPU does not waste time in a polling loop.
• Better CPU utilization: The CPU performs useful work while waiting for the slow device.
• Faster response: Devices are serviced promptly when they become ready.

Identifying the interrupt source: Two methods are used:

• Software (Polling): The CPU polls each device to find who interrupted.
• Hardware (Vectored Interrupt): The interrupting device supplies a vector address that directs the CPU straight to the correct ISR.

Priority Interrupt:
A priority interrupt is a system that establishes a priority order among various interrupt sources to determine which device should be serviced first when several devices request service simultaneously. Devices with higher speed or higher urgency are given higher priority.

Daisy-Chaining Priority (Hardware method):

The daisy-chain method connects all devices that request interrupts in series, according to their priority. The device closest to the CPU has the highest priority.

CPU --INT--> [Dev 1] --> [Dev 2] --> [Dev 3]
<--INTACK (PI/PO chain)
PI=Priority In, PO=Priority Out

Working:

• All devices share a common interrupt line to the CPU.
• The CPU responds with an interrupt acknowledge (INTACK) signal that propagates through the chain.
• Each device has a Priority In (PI) and Priority Out (PO).
  • If a device with is not requesting an interrupt, it passes the acknowledge to the next device by setting .
  • If a device with is requesting, it blocks the signal by setting , places its Vector Address (VAD) on the bus, and gets serviced.

Advantages:

• Simple hardware, fewer control lines.

Disadvantages:

• Priority is fixed by physical position.
• If a device near the CPU fails, it may block lower-priority devices.

Parallel Priority Interrupt:

This method uses a register (the interrupt register) whose bits are set separately by the interrupting devices. Priority is established according to the bit position in the register.

Components:

• Interrupt Register (IEN bits): Each bit corresponds to one interrupt source. A bit is set when the corresponding device requests service.
• Mask Register: Has a bit for each interrupt source. It is used to enable or disable individual interrupts. The interrupt register is ANDed with the mask register.
• Priority Encoder: Determines the highest-priority request among all active, unmasked interrupts and generates a binary code identifying that device.
• Interrupt Enable Flip-Flop (IEN): Globally enables/disables the interrupt system.

Working:

1. Devices set their respective bits in the interrupt register.
2. The interrupt register output is masked (ANDed with mask register) to ignore disabled interrupts.
3. The priority encoder produces the vector address of the highest-priority active interrupt.
4. An Interrupt Status Flip-Flop (IST) is set, sending an interrupt to the CPU.
5. The CPU services the highest-priority device.

Advantages over daisy-chaining:

• Priority can be dynamically changed using the mask register.
• Faster response since priority resolution is done in parallel.
• More flexible control over individual interrupts.

Direct Memory Access (DMA):

DMA is a technique in which data is transferred directly between an I/O device and main memory without continuous involvement of the CPU. A special hardware unit called the DMA controller manages the transfer.

Need for DMA:

• In programmed and interrupt I/O, the CPU transfers each word, which is slow for bulk/high-speed data (e.g., disks).
• DMA removes the CPU from the data path, greatly increasing transfer speed.

Working:

1. The CPU initializes the DMA controller by writing:
   • Starting address of the memory block (Address register).
   • Word count — number of words to transfer (Count register).
   • Control information — direction of transfer (read/write).
2. The DMA controller sends a Bus Request (BR) to the CPU.
3. The CPU responds with a Bus Grant (BG), relinquishing control of the address bus, data bus, and control lines by placing them in a high-impedance state.
4. The DMA controller now becomes the bus master and transfers data directly between the device and memory.
5. After transferring the block, the DMA controller releases the buses and sends an interrupt to the CPU signaling completion.

Advantages:

• Very fast data transfer.
• Frees the CPU for other tasks during transfer.
• Ideal for high-speed devices and large data blocks.

The DMA controller transfers data in two main modes:

1. Burst Transfer (Block Transfer):

• A block of data (a series of memory words) is transferred in a continuous sequence.
• The DMA controller takes complete control of the buses and transfers all words of the block without interruption.
• The CPU is suspended for the entire duration of the transfer.
• Advantage: Very fast; efficient for high-speed devices such as magnetic disks where data must be transferred quickly.
• Disadvantage: The CPU cannot access the bus during the transfer.

2. Cycle Stealing:

• The DMA controller transfers one word at a time, then returns bus control to the CPU.
• The DMA "steals" a memory cycle from the CPU whenever it needs to transfer a word.
• The CPU is only delayed slightly (one memory cycle per word) and continues in between.
• Advantage: The CPU is not fully blocked; it can continue operating between transfers.
• Disadvantage: Slower overall transfer rate than burst mode.

Comparison:

DMA Controller Block Diagram:

       Address bus

DMA request DS RS BR BG Interrupt
DMA acknowl. RD WR (to/from CPU)

Major Registers:

• Address Register: Holds the starting address of the memory location for read/write. It is incremented after each word transfer.
• Word Count Register: Holds the number of words to be transferred. It is decremented after each transfer; when it reaches zero, the transfer stops.
• Control Register: Specifies the mode of transfer (read or write) and other control information.

Control Signals:

• DS (DMA Select) and RS (Register Select): Used by the CPU to select the DMA and its internal registers during initialization.
• RD (Read) and WR (Write): Determine the direction of transfer.
• BR (Bus Request) and BG (Bus Grant): Used to request and grant control of the system buses.
• Interrupt: Sent to the CPU when the transfer is complete.
• DMA Request / DMA Acknowledge: Communication with the I/O device.

Operation: The CPU initializes the registers, then the DMA controller autonomously transfers data between the device and memory, updating the address and count registers until completion.

UART (Universal Asynchronous Receiver Transmitter):

A UART is a hardware device (or circuit) that handles asynchronous serial communication. It converts parallel data from the CPU into serial form for transmission and converts received serial data back into parallel form.

Main Functions:

• Transmitter section: Accepts parallel data from the CPU, adds framing bits (start, stop, parity), and transmits the data serially, one bit at a time.
• Receiver section: Receives serial data, removes framing bits, checks parity, and assembles the bits into parallel data for the CPU.

Asynchronous Serial Transmission Format:

Each character is framed as follows:

• Start bit: A single bit (logic 0) that signals the beginning of a character. The line is normally at logic 1 (idle).
• Data bits: The actual character (typically 5 to 8 bits), sent least significant bit first.
• Parity bit (optional): Used for error detection (even or odd parity).
• Stop bit(s): One or two bits (logic 1) that mark the end of the character.

Idle | Start | D0 D1 D2 ... D7 | Parity | Stop | Idle
(1) | (0) | data bits | | (1) |

Key Points:

• "Asynchronous" means no separate clock is transmitted; sender and receiver agree on a baud rate.
• The start and stop bits synchronize the receiver for each character.
• UART is used in serial ports, modems, and microcontroller communication.

Synchronous vs Asynchronous Serial Transmission:

Asynchronous Transmission:

• Data is transmitted character by character.
• Each character is preceded by a start bit and followed by stop bit(s).
• The receiver resynchronizes at the start of every character.
• Suitable for low-speed, irregular data.

Synchronous Transmission:

• Data is transmitted as a continuous stream of bits synchronized by a common clock.
• Special sync characters mark the beginning of a block.
• More efficient for large volumes of data at high speed.

Input/Output Processor (IOP):

An IOP is a specialized processor dedicated to handling all I/O operations, relieving the CPU of I/O responsibilities. It can be considered a processor with direct memory access capability that communicates with I/O devices.

Role of the IOP:

• Fetches and executes its own set of I/O instructions (called commands or programs) from memory.
• Manages the transfer of data between peripherals and memory independently.
• Handles device details such as data formatting, error checking, and control.
• The CPU and IOP communicate through memory and control signals.

IOP vs DMA Controller:

CPU-IOP Communication:

• The CPU instructs the IOP to start an I/O program.
• The IOP executes the program, transfers data, and interrupts the CPU when done.
• This is common in large computer systems where I/O is heavy (channel-based I/O in mainframes).

CPU-IOP Communication:

The communication between the CPU and the I/O Processor (IOP) is a coordinated process where each unit performs its designated tasks. They communicate primarily through memory.

CPU IOP ---- Peripheral Devices
| |
(control/status signals)

Sequence of Operations:

1. CPU checks IOP status: The CPU tests whether the IOP is available to perform I/O.
2. CPU sends instruction: The CPU sends a command to the IOP to start executing an I/O program stored in memory.
3. IOP executes program: The IOP retrieves the program from memory and carries out the I/O operations, transferring data between the peripheral and memory.
4. IOP checks status: The IOP monitors device status and manages data transfer, formatting, and error checking.
5. IOP interrupts CPU: When the I/O operation completes, the IOP sends an interrupt to the CPU.
6. CPU responds: The CPU checks the IOP status word (stored in memory) to determine whether the operation was successful.

Key Points:

• The CPU and IOP work concurrently, improving overall system throughput.
• Communication is done via memory-resident control/status words and interrupts.
• This model is used in large systems where the IOP is called an I/O channel.

Comparison of Data Transfer Modes:

Explanation:

• Programmed I/O: The CPU executes instructions to check status and transfer each word. Simple but wasteful.
• Interrupt-Driven I/O: The device interrupts the CPU only when ready, so the CPU does useful work in between. Better efficiency.
• DMA: Data moves directly between memory and the device via a DMA controller, with the CPU freed almost entirely. Best for large, fast transfers.

Conclusion: As we move from programmed I/O to DMA, CPU involvement decreases while transfer speed and hardware complexity increase.

Interrupt Processing by the CPU:

When the CPU receives an interrupt request, it follows these steps:

1. Finish current instruction: The CPU completes execution of the currently executing instruction.
2. Acknowledge the interrupt: The CPU sends an acknowledge signal to the interrupting device.
3. Save context: The CPU saves the program counter (PC) and the processor status word (PSW) onto the stack.
4. Load ISR address: The CPU loads the address of the Interrupt Service Routine (ISR) into the PC (via a vector address or fixed location).
5. Execute ISR: The CPU executes the ISR to service the device.
6. Restore context: After the ISR completes, the saved PC and PSW are restored from the stack.
7. Resume: The CPU resumes the interrupted program.

Types of Interrupts:

• External Interrupts: Come from I/O devices, timers, or external sources (e.g., keyboard, disk).
• Internal Interrupts (Traps): Arise from illegal or erroneous use of an instruction (e.g., divide by zero, invalid opcode, stack overflow). These are synchronous with the program.
• Software Interrupts: Initiated by executing a special instruction (e.g., system calls / INT instruction).

Further classification:

• Maskable interrupts: Can be enabled/disabled by the programmer.
• Non-maskable interrupts (NMI): Cannot be disabled; used for critical events (e.g., power failure).

Priority Encoder:

A priority encoder is a combinational circuit that accepts multiple interrupt request inputs and produces a binary code corresponding to the highest-priority active input. It ensures that when multiple interrupts occur simultaneously, only the highest-priority one is recognized.

4-Input Priority Encoder Truth Table:

(Inputs where has highest priority; outputs ; = valid/IST)

(X = don't care)

Boolean Expressions:

Explanation:

• The output gives the binary vector of the highest-priority active interrupt.
• The valid bit is set to 1 when at least one input is active; it signals the CPU that an interrupt is pending.
• The 2-bit output () can be used along with a base address to form the vector address (VAD) of the corresponding ISR.

Use in interrupt system: The encoder output combined with the interrupt/mask registers determines which device the CPU services first, enabling fast parallel priority resolution.

Asynchronous Data Transfer:

When two units operate at different clock rates and are not synchronized, asynchronous transfer methods are used. Two common techniques are strobe control and handshaking.

1. Strobe Control:

• Uses a single control line (strobe) to indicate the time at which data is being transferred.
• The strobe may be activated by either the source or destination unit.
• Source-initiated: The source places data on the bus and activates the strobe; the destination reads the data.
• Destination-initiated: The destination activates the strobe requesting data; the source responds with data.
• Disadvantage: No way to confirm that the data was actually received (no acknowledgment).

2. Handshaking:

• Uses two control lines — one for the source and one for the destination.
• Provides mutual confirmation: the receiving unit acknowledges receipt of data.
• Example (source-initiated): Source places data and asserts Data Valid; destination reads data and asserts Data Accepted; source then removes data.
• Advantage: High flexibility and reliability; each unit informs the other of its status.

Comparison:

Conclusion: Handshaking is more reliable because it confirms the completion of each transfer, whereas strobe control assumes the transfer succeeds.