Unit 4: Input-Output Organization

The I/O subsystem connects the CPU and memory to the outside world, reconciling the fast, synchronous internal bus with slow, diverse, asynchronous external devices. Every mechanism in this unit exists to bridge that speed and format mismatch while freeing the processor to compute.

• Central problem: The CPU cycles in nanoseconds; a keyboard or disk responds in milliseconds. Direct byte-by-byte servicing would waste billions of cycles.
• Bus structure: A shared system bus carries an address bus, data bus and control bus; interfaces sit between this bus and each device.
• Addressing conventions: Devices are reached either by isolated I/O (separate I/O address space, distinct IN/OUT instructions) or memory-mapped I/O (device registers occupy normal memory addresses, using ordinary load/store).
• Core concerns carried forward: synchronization, priority, and who owns the bus during a transfer.

II. Peripheral Devices — Sources and Sinks of Data

Peripherals are the external units that supply input, accept output, or store data outside main memory.

A. Classification and Characteristics

• Input devices: keyboard, mouse, scanner — convert human or physical signals into binary.
• Output devices: monitor, printer, plotter — convert binary into human-readable form.
• Storage (I/O) devices: magnetic disk, SSD, tape — both read and write.
• Data representation: alphanumeric peripherals use ASCII (7 bits, 128 codes) or extended 8-bit codes.

B. Electromechanical vs Electronic Nature

1. Electromechanical devices: printers, disks — governed by moving parts, hence millisecond latencies.
2. Purely electronic devices: display controllers — faster, limited by circuit and refresh timing.

• Consequence: the wide range of speeds and codes forces every peripheral to connect through an interface rather than to the bus directly.

III. Input–Output Interface — The Bridge Circuit

An I/O interface is the hardware between a peripheral and the system bus that resolves differences in signal, speed, code, and control.

A. Purpose and Principle

• Signal conversion: adapts device voltage/format to bus logic levels.
• Synchronization: buffers data so the fast CPU and slow device need not run in lockstep.
• Code resolution: reconciles device word length with CPU word length.

B. Interface Registers and Bus Connection

• Data register: holds the byte in transit.
• Status register: flags such as ready, busy, error.
• Control register: receives commands (start read, start write).
• Address decoder: compares bus address lines against the interface's assigned address; a match asserts chip-select.

CPU <--> System Bus <--> [ Address decoder ]
                         [ Control reg ]
                         [ Status reg  ] <--> Peripheral
                         [ Data reg    ]

C. Isolated vs Memory-Mapped I/O

1. Isolated I/O: separate address space; needs IN/OUT; more instructions but full memory range preserved.
2. Memory-mapped I/O: device registers treated as memory; any memory-reference instruction manipulates them, at the cost of consuming address space.

IV. Modes of Data Transfer — CPU, Interrupt, and DMA

The three modes differ in how the CPU learns a device is ready and who moves the data.

A. Programmed I/O

• Principle: the CPU repeatedly reads the status register in a loop (polling) until the ready flag sets, then transfers one word.
• Cost: the CPU is fully occupied while waiting — wasteful for slow devices.

loop: read status
      if flag = 0 goto loop
      read data register

B. Interrupt-Initiated I/O

• Principle: the CPU issues the command and continues other work; the interface raises an interrupt when ready.
• Response: CPU finishes the current instruction, saves the program counter, and vectors to a service routine.
• Benefit: no busy-waiting, so CPU utilization rises.

C. Direct Memory Access

• Principle: a dedicated controller transfers data straight between device and memory, bypassing the CPU per-word.

• Placement: used for high-speed block devices (disk, network); detailed in Section VI.

• Comparison anchor: for an n-byte block, programmed and interrupt I/O incur per-byte CPU overhead; DMA incurs it once per block.

V. Priority Interrupt — Ordering Simultaneous Requests

A priority interrupt system decides which of several pending interrupts the CPU services first.

A. Purpose and Principle

• Need: multiple devices may interrupt at once; higher-urgency or faster devices must be served first.
• Rule: a higher-priority request may interrupt a lower-priority routine already running (nesting).

B. Software (Polling) Priority

• Method: a single interrupt line; the service routine polls each source in a fixed order.
• Order = priority: the first device tested has highest priority.
• Drawback: polling time grows with the number of devices.

C. Hardware Priority — Daisy Chain and Parallel

1. Daisy-chain (serial): devices connected in series on the acknowledge line; the nearest device to the CPU has highest priority and passes the signal along only if it did not request.
   • PI/PO logic: each device has priority-in and priority-out; PO = 0 blocks all downstream devices.
2. Parallel priority: a register of interrupt bits feeds a priority encoder; a mask register can enable or disable each source independently, giving faster and programmable priority.

D. Interrupt Cycle and Vectored Interrupt

• Interrupt cycle: after each instruction the CPU checks the interrupt flip-flop; if set, it stores the return address and branches.
• Vectored interrupt: the interrupting device supplies a vector address (via the VAD), pointing directly to its service routine — faster than polling.

VI. Direct Memory Access Transfer — Bulk Movement Without the CPU

DMA lets an external controller move data blocks between memory and a peripheral, using the buses while the CPU is idle on them.

A. Purpose and Principle

• Goal: eliminate per-word CPU intervention for high-throughput transfers.
• Bus handover: the DMA controller requests the bus; the CPU relinquishes it and floats its bus lines.

B. Bus Control Signals

• Bus Request (BR): DMA asks the CPU for the bus.
• Bus Grant (BG): CPU replies, releasing address, data, and read/write lines.
• Cycle stealing: DMA takes single bus cycles between CPU accesses; alternatively burst mode seizes the bus for a whole block.

C. DMA Controller Registers and Transfer

• Address register: holds the current memory address; auto-incremented after each word.
• Word-count register: number of words remaining; decremented to zero.
• Control register: read/write direction and start.

Init:  address reg <- start
       word count  <- N
Repeat: transfer word; address++; count--
Until:  count = 0 -> interrupt CPU (done)

• Worked example: to move 512 words to memory from address 2000, load address = 2000 and count = 512; the controller writes words 2000…2511, then interrupts the CPU once at completion — a single interrupt versus 512 under interrupt I/O.

VII. UART — Universal Asynchronous Receiver–Transmitter

A UART converts between the CPU's parallel data and a serial line, framing each character asynchronously.

A. Purpose and Principle

• Serial need: long-distance and low-pin links transmit one bit at a time; the UART serializes and deserializes.
• Asynchronous: no shared clock; each character is self-framed by start and stop bits.

B. Frame Format and Baud Rate

• Start bit: one bit, logic 0, marks the beginning after an idle high line.
• Data bits: typically 7 or 8, sent least-significant-bit first.
• Parity bit: optional even/odd error check.
• Stop bit(s): one or two logic-1 bits close the frame.
• Baud rate: bits per second (e.g. 9600); transmitter and receiver must agree beforehand.

C. Transmitter and Receiver Sections

1. Transmitter: loads a parallel byte into a shift register, appends start/parity/stop, and shifts it out at the baud clock.
2. Receiver: detects the start-bit edge, samples each bit at mid-interval, strips framing bits, checks parity, and presents the assembled byte to the CPU.

• Error flags: framing error (missing stop bit), parity error, overrun (byte not read before the next arrives).

VIII. Input/Output Processor — Offloading I/O to a Dedicated CPU

An IOP is a specialized processor that executes its own I/O programs, relieving the main CPU of transfer management entirely.

A. Purpose and Principle

• Autonomy: the IOP fetches and runs I/O instructions from memory, handling device addressing, formatting, and error checking on its own.
• Communication: CPU and IOP exchange status through shared memory and command words rather than per-word signals.

B. CPU–IOP Communication Sequence

• CPU: places an I/O program and command in memory, then signals the IOP to start.
• IOP: executes the program, transfers the block, and upon finishing sets a status word and interrupts the CPU.
• Handshake: CPU tests the status word to confirm completion or detect error.

C. Relation to DMA and Channels

1. DMA: hardware-controlled, moves a preset block; parameters loaded by the CPU.
2. IOP (channel): program-controlled, decides sequences of transfers itself, capable of servicing many devices and complex sequences — a step above DMA in independence.

• Result: in large systems the IOP acts as a channel, letting the main CPU concentrate on computation while I/O proceeds concurrently.