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Unit 5: Memory Unit - Practice Quiz

CSE211 — Computer Organization And Design 60 Questions
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1 In the memory hierarchy, which memory is typically the fastest but has the smallest storage capacity?

Memory hierarchy Easy
A. Magnetic tape
B. Registers
C. Magnetic disk
D. Main memory

2 As we move down the memory hierarchy from CPU registers toward auxiliary memory, the cost per bit generally:

Memory hierarchy Easy
A. Decreases
B. Remains constant
C. Becomes zero
D. Increases

3 The primary purpose of cache memory is to:

Cache memory Easy
A. Provide permanent data storage
B. Speed up access to frequently used data
C. Replace the hard disk
D. Increase the total memory size

4 When the CPU finds the required data in the cache, the event is called a:

Cache memory Easy
A. Cache flush
B. Page fault
C. Cache miss
D. Cache hit

5 Cache memory is usually built using which type of memory technology?

Cache memory Easy
A. DRAM
B. Magnetic core
C. Flash memory
D. SRAM

6 Virtual memory allows a program to:

Virtual memory Easy
A. Use more memory than physically available
B. Avoid using the hard disk
C. Skip the memory hierarchy
D. Run faster than the CPU clock

7 In virtual memory, a fixed-size block of the logical address space is called a:

Virtual memory Easy
A. Sector
B. Page
C. Cache line
D. Register

8 A page fault occurs when:

Virtual memory Easy
A. The cache is full
B. The CPU register overflows
C. The required page is not in main memory
D. Two pages have the same address

9 Main memory in a computer is also commonly known as:

Main memory Easy
A. RAM
B. Hard disk
C. Cache
D. ROM only

10 Which characteristic best describes main memory (RAM)?

Main memory Easy
A. Non-volatile
B. Read-only
C. Volatile
D. Sequential access only

11 Which of the following is an example of auxiliary memory?

Auxiliary memory Easy
A. Magnetic disk
B. Cache memory
C. CPU register
D. Instruction decoder

12 Auxiliary memory is characterized by being:

Auxiliary memory Easy
A. Directly accessed by the CPU
B. Non-volatile with large capacity
C. Faster than cache
D. Volatile with small capacity

13 In the write-through technique, data is written to:

Writing into Cache concept Easy
A. Only the auxiliary memory
B. Both cache and main memory simultaneously
C. Only the CPU registers
D. Only the cache

14 In the write-back technique, main memory is updated:

Writing into Cache concept Easy
A. Never at all
B. Before the cache is updated
C. On every write operation
D. Only when the cache block is replaced

15 Which cache mapping technique allows a memory block to be placed in any cache line?

Mapping Techniques Easy
A. Sequential mapping
B. Set-associative mapping
C. Associative mapping
D. Direct mapping

16 In direct mapping, each block of main memory maps to:

Mapping Techniques Easy
A. Exactly one cache line
B. Any cache line
C. Two cache lines
D. No cache line

17 The main goal of parallel processing is to:

Introduction to Parallel Processing Easy
A. Eliminate the CPU
B. Increase computational speed
C. Slow down execution
D. Reduce memory size

18 Pipelining improves processor performance by:

Pipelining Easy
A. Removing the control unit
B. Increasing the clock cycle time
C. Overlapping the execution of multiple instructions
D. Reducing the number of registers

19 A multiprocessor system is one that contains:

Characteristics of Multiprocessors Easy
A. Only memory units
B. A single CPU only
C. Two or more CPUs sharing resources
D. No control unit

20 Which interconnection structure uses a single shared path for all processors and memory modules?

Interconnection Structures Easy
A. Multiport memory
B. Crossbar switch
C. Common bus system
D. Hypercube network

21 In a typical memory hierarchy, as you move from the CPU registers down toward auxiliary memory, which combination of properties correctly describes the trend?

Memory hierarchy Medium
A. Access time increases, cost per bit decreases, capacity increases
B. Access time decreases, cost per bit increases, capacity decreases
C. Access time increases, cost per bit increases, capacity decreases
D. Access time decreases, cost per bit decreases, capacity increases

22 A program has a cache hit ratio of . The cache access time is ns and main memory access time is ns. What is the average memory access time?

Cache memory Medium
A. ns
B. ns
C. ns
D. ns

23 A direct-mapped cache has blocks. To which cache line does main memory block number map?

Mapping Techniques Medium
A. Line
B. Line
C. Line
D. Line

24 In a paged virtual memory system, what is the primary function of the page table?

Virtual memory Medium
A. Map virtual page numbers to physical frame numbers
B. Store the actual contents of pages on disk
C. Convert physical addresses into logical addresses
D. Hold the most recently used cache blocks

25 Which statement best distinguishes the write-back policy from the write-through policy?

Writing into Cache concept Medium
A. Write-back updates memory on every write, while write-through updates it only on eviction
B. Write-back updates memory only when the block is evicted, while write-through updates memory on every write
C. Both update memory on every write but differ in cache line size
D. Write-back never updates main memory under any condition

26 A non-pipelined processor takes ns per instruction. A -stage pipeline divides this into equal stages. Ignoring hazards and overhead, what is the ideal throughput speedup for a very large number of instructions?

Pipelining Medium
A. times
B. times
C. times
D. times

27 In a set-associative cache with -way associativity and sets, which set does main memory block map to?

Mapping Techniques Medium
A. Set
B. Set
C. Set
D. Set

28 For a magnetic disk, which factor primarily determines the seek time?

Auxiliary memory Medium
A. Rate at which data is transferred to memory
B. Time to decode the disk controller command
C. Time to move the read/write head to the desired track
D. Time for the desired sector to rotate under the head

29 A main memory of size KB is byte-addressable. How many bits are required for the memory address?

Main memory Medium
A. bits
B. bits
C. bits
D. bits

30 Which characteristic distinguishes a tightly coupled multiprocessor from a loosely coupled one?

Characteristics of Multiprocessors Medium
A. Each processor has only private memory with no sharing at all
B. Only a single processor can be active at any given time
C. Processors communicate exclusively through message passing over a network
D. Processors share a common global memory through a shared bus or interconnection

31 The principle that recently accessed memory locations are likely to be accessed again soon is known as:

Cache memory Medium
A. Associative mapping
B. Temporal locality
C. Sequential access
D. Spatial locality

32 In a crossbar switch interconnection connecting processors to memory modules, how many crosspoint switches are required?

Interconnection Structures Medium
A.
B.
C.
D.

33 A system uses a virtual address space of bits with a page size of KB. How many entries does a single-level page table contain?

Virtual memory Medium
A. entries
B. entries
C. entries
D. entries

34 Which type of pipeline hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed?

Pipelining Medium
A. Data hazard
B. Timing hazard
C. Structural hazard
D. Control hazard

35 Which cache mapping technique requires comparing the tag with all cache lines simultaneously, needing the most comparison hardware?

Mapping Techniques Medium
A. Direct mapping
B. Two-way set-associative mapping
C. Sector mapping
D. Fully associative mapping

36 According to Flynn's classification, a system where a single instruction stream operates on multiple data streams is categorized as:

Introduction to Parallel Processing Medium
A. SIMD
B. MIMD
C. SISD
D. MISD

37 A cache miss that occurs because a block was evicted earlier and is now referenced again, in a cache that is not large enough to hold the working set, is called a:

Cache memory Medium
A. Coherence miss
B. Compulsory miss
C. Capacity miss
D. Conflict miss

38 Why is DRAM used for main memory while SRAM is typically used for cache?

Main memory Medium
A. DRAM needs no refresh, while SRAM requires constant refreshing
B. DRAM is faster and denser, while SRAM is slower but cheaper
C. DRAM is cheaper and denser, while SRAM is faster but more expensive
D. DRAM is non-volatile, while SRAM loses data on power off

39 In a time-shared common bus interconnection for multiprocessors, what is the primary limitation as the number of processors increases?

Interconnection Structures Medium
A. Bus contention limits throughput since only one transfer can occur at a time
B. The number of crosspoint switches grows quadratically
C. Memory modules must double in size for each processor added
D. Each processor loses access to its private cache

40 The special cache that stores recently used page-table entries to speed up address translation is called the:

Virtual memory Medium
A. Translation Lookaside Buffer (TLB)
B. Page Fault Buffer
C. Memory Management Register
D. Segment Descriptor Cache

41 A processor has a cache with a hit time of ns, a miss penalty of ns, and a hit rate of . If a second-level cache is added with an access time of ns and a local hit rate of (for accesses that miss L1), what is the new average memory access time (AMAT)?

Cache memory Hard
A. ns
B. ns
C. ns
D. ns

42 A cache has blocks with a -way set-associative organization. The main memory has blocks. To which set does memory block number map?

Mapping Techniques Hard
A. Set
B. Set
C. Set
D. Set

43 A system uses a -bit virtual address and KB pages. If the page table entry is bytes, what is the size of a single-level page table?

Virtual memory Hard
A. GB
B. MB
C. MB
D. MB

44 A non-pipelined processor takes ns per instruction. A -stage pipeline is built with stage delays of , and ns, plus a ns latch delay per stage. What is the maximum speedup for a very large number of instructions?

Pipelining Hard
A.
B.
C.
D.

45 In a memory hierarchy, the effective access time is for a two-level system. If ns, ns, and the required must be at most ns, what is the minimum hit ratio ?

Memory hierarchy Hard
A.
B.
C.
D.

46 Consider a write-back cache with a dirty bit. Which scenario correctly describes when a main-memory write actually occurs?

Writing into Cache concept Hard
A. Only on a read miss to a clean block
B. On every store instruction issued by the CPU regardless of cache state
C. Whenever any cache block is loaded from memory
D. Only when a dirty block is evicted from the cache

47 A direct-mapped cache has lines, each of bytes, and the memory is byte-addressable with -bit addresses. How many bits are used for the tag field?

Cache memory Hard
A. bits
B. bits
C. bits
D. bits

48 In a multiprocessor using a crossbar switch to connect processors to memory modules, how many switch points (crosspoints) are required, and what is the main limitation?

Interconnection Structures Hard
A. crosspoints; only processors contend
B. crosspoints; latency dominates
C. crosspoints; contention grows linearly
D. crosspoints; hardware cost grows quadratically, limiting scalability

49 A main memory is built from modules using low-order (word) interleaving. If a program accesses addresses sequentially, which statement is true about module utilization?

Main memory Hard
A. Only even-numbered modules are used for sequential access
B. Consecutive words fall in the same module, causing serialization
C. Consecutive words fall in different modules, maximizing overlap for sequential access
D. Interleaving has no effect on sequential access patterns

50 Which statement best distinguishes a tightly coupled multiprocessor from a loosely coupled one?

Characteristics of Multiprocessors Hard
A. Tightly coupled systems use message passing whereas loosely coupled systems share global memory
B. Tightly coupled systems share a common memory and communicate through it, while loosely coupled systems have local memories and communicate via message passing
C. Both share a single memory but differ in clock speed only
D. Loosely coupled systems always outperform tightly coupled systems

51 A -stage pipeline executes instructions. Due to data hazards, every th instruction stalls for cycles. For instructions, approximately how many clock cycles are needed (ignore initial fill beyond the standard )?

Pipelining Hard
A. cycles
B. cycles
C. cycles
D. cycles

52 A magnetic disk rotates at RPM. What is the average rotational latency?

Auxiliary memory Hard
A. ms
B. ms
C. ms
D. ms

53 For a fully associative cache with blocks using LRU replacement, what is the primary hardware cost compared to a direct-mapped cache of the same size?

Mapping Techniques Hard
A. It uses fewer tag bits and no comparators at all
B. It requires comparing the tag against all blocks in parallel plus LRU tracking logic, greatly increasing complexity and cost
C. It requires only one comparator and a simple index decoder
D. It eliminates the need for a valid bit per block

54 A TLB has a hit rate of and access time of ns. A TLB miss requires a page-table walk costing ns. Assuming the actual memory access after translation is ns and pages are always in memory, what is the effective memory access time?

Virtual memory Hard
A. ns
B. ns
C. ns
D. ns

55 According to Flynn's taxonomy, a vector processor that applies one instruction across multiple data elements simultaneously is best classified as:

Introduction to Parallel Processing Hard
A. SISD
B. MIMD
C. SIMD
D. MISD

56 Using Amdahl's Law, if of a program can be parallelized and it runs on processors, what is the maximum speedup?

Introduction to Parallel Processing Hard
A.
B.
C.
D.

57 In a write-through cache with a write buffer, what problem can arise, and how is it typically mitigated?

Writing into Cache concept Hard
A. A subsequent read miss may need data still sitting in the write buffer, so the buffer is checked (snooped) on read misses before going to memory
B. The write buffer must be flushed on every read, eliminating any performance benefit
C. Write-through can never cause read hazards because memory is always current instantly
D. Reads bypass the buffer entirely and always read the most recent value from cache

58 A multistage interconnection network (MIN) connects inputs to outputs using switches. How many stages and how many switches per stage are required for an Omega network?

Interconnection Structures Hard
A. stages, switches per stage
B. stages, switches per stage
C. stages, switches per stage
D. stages, switches per stage

59 Which combination correctly orders the levels of the memory hierarchy from fastest/smallest to slowest/largest?

Memory hierarchy Hard
A. Registers → Main memory → Cache → Auxiliary memory
B. Main memory → Cache → Registers → Auxiliary memory
C. Registers → Cache → Main memory → Auxiliary memory
D. Cache → Registers → Auxiliary memory → Main memory

60 A program repeatedly accesses two arrays whose addresses map to the same direct-mapped cache line, alternating between them. This causes which phenomenon, and which change would eliminate it?

Cache memory Hard
A. Coherence misses; adding a write buffer would solve it
B. Compulsory misses; increasing the block size would remove them
C. Conflict misses (thrashing); using a set-associative cache would allow both blocks to reside simultaneously
D. Capacity misses; reducing the cache size would help
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