Unit 3: Central Processing Unit - Subjective Questions

General Register Organization uses a set of registers connected through a common bus system, allowing fast data transfer between registers and the ALU without repeated memory access.

Key Components:

• A set of general-purpose registers (e.g., )
• Two multiplexers (MUX A and MUX B) to select source registers
• An ALU to perform arithmetic and logic operations
• A decoder to select the destination register

Operation:

• The output of each register is connected to two multiplexers to form the two buses A and B.
• The selection lines of the MUXes choose which register drives each bus.
• Bus A and Bus B provide the two operands to the ALU.
• The ALU performs the operation specified by the operation select lines.
• The result is routed back to a destination register selected by the decoder.

Example micro-operation:

This requires:

• MUX A selects
• MUX B selects
• ALU performs addition
• Decoder selects as destination

Advantages:

• Reduces memory traffic
• Enables faster execution
• Efficient for expression evaluation

The control word for such an organization has fields for SELA, SELB, SELD/SELREG, and OPR (operation).

Control Word: A control word is a binary word that specifies a micro-operation by encoding the selection of source registers, destination register, and the ALU operation.

Field Structure (14 bits):

Encoding for registers:

• = Input, , , , etc.

For :

• SELA = =
• SELB = =
• SELD = =
• OPR = SUB = (example encoding)

Complete Control Word:

Explanation:

• MUX A selects onto Bus A
• MUX B selects onto Bus B
• ALU subtracts B from A
• Decoder routes result to

A stack is a Last-In-First-Out (LIFO) storage device where items are inserted and removed from the same end called the top of stack (TOS).

Basic Operations:

• PUSH: Insert an item onto the stack
• POP: Remove an item from the stack

1. Register Stack:
A finite set of registers organized as a stack. A Stack Pointer (SP) register holds the address of the top element.

PUSH operation:

• If after push, stack is FULL.

POP operation:

• If after pop, stack is EMPTY.

• Uses FULL and EMPTY flags to indicate stack status.

• Limited depth (fixed number of registers).

2. Memory Stack:
A portion of main memory is used as a stack. The SP points to the top of the stack within memory.

PUSH:

POP:

Difference:

Reverse Polish Notation (RPN), also known as postfix notation, places the operator after the operands. It requires no parentheses and is ideal for stack-based evaluation.

Infix:

Postfix Conversion:

Stack Evaluation Procedure:

• Scan the postfix expression left to right.
• Operand → push onto stack.
• Operator → pop two operands, apply operator, push result back.

Step-by-step (assume ):

Result:

Advantages:

• No need for parentheses or precedence rules
• Efficient hardware implementation using a stack

Addressing modes specify how the operand of an instruction is chosen at execution time. They provide flexibility in accessing data.

1. Implied Mode:

• Operand is specified implicitly in the instruction.
• Example: CMA (Complement Accumulator) — operand is the accumulator.

2. Immediate Mode:

• Operand is part of the instruction itself.
• Example: MOV R1, #5 → loads constant 5.

3. Register Mode:

• Operand is in a register; instruction contains register address.
• Example: MOV R1, R2.

4. Register Indirect Mode:

• Register holds the address of the operand in memory.
• Effective Address: .

5. Autoincrement/Autodecrement Mode:

• Register is automatically incremented/decremented after/before access.
• Useful for array traversal.

6. Direct (Absolute) Mode:

• Address field contains the effective address of the operand.
• .

7. Indirect Mode:

• Address field points to a memory location containing the effective address.
• .

8. Relative Address Mode:

• Effective address = Program Counter + Address field.
• .

9. Indexed Addressing Mode:

• .

10. Base Register Mode:

• ; used in relocation.

Assume the instruction is at address with an address field value of . After fetch, (points to next instruction). For clarity, we use for relative addressing.

1. Direct Addressing:

• Operand =

2. Immediate Addressing:

• Operand = (the address field itself)

3. Indirect Addressing:

• Operand =

4. Relative Addressing:

• Operand = (memory content at 701)

5. Indexed Addressing:

• Operand =

6. Register Addressing:

• Operand =

7. Register Indirect Addressing:

• Operand = (content at 400)

Summary Table:

RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) represent two contrasting CPU design philosophies.

Comparison Table:

RISC Advantages:

• Simple instructions enable efficient pipelining
• Faster execution per instruction
• Simpler and cheaper hardware

RISC Disadvantages:

• Larger program (code) size
• Increased memory bandwidth demand

CISC Advantages:

• Compact code (fewer instructions per task)
• Rich instruction set eases compiler design

CISC Disadvantages:

• Complex hardware
• Difficult to pipeline
• Variable execution times

Examples: RISC — ARM, MIPS, SPARC. CISC — Intel x86, VAX.

RISC (Reduced Instruction Set Computer) emphasizes simplicity and speed through a reduced set of simple instructions.

Key Characteristics:

• Relatively few instructions: A small, carefully chosen instruction set.
• Few addressing modes: Simplifies instruction decoding.
• Fixed-length, easily decoded instruction format: All instructions same size, aligned in memory.
• Single-cycle instruction execution: Most instructions complete in one clock cycle.
• Memory access limited to LOAD and STORE: Only these instructions access memory; all others operate on registers (Load/Store architecture).
• Large number of registers: Reduces memory access and supports register windows.
• Hardwired control unit: Faster than microprogrammed control.
• Register-to-register operations: Arithmetic/logic operations use registers only.

Why RISC supports efficient pipelining:

• Fixed instruction length allows instructions to be fetched and decoded uniformly in the pipeline.
• Simple instructions complete in a single cycle, avoiding pipeline stalls.
• Load/Store architecture decouples memory access from computation, reducing hazards.
• Few addressing modes simplify the decode stage.
• Register-based operations avoid frequent memory delays.

These features make it easy to overlap the fetch, decode, execute, memory, and write-back stages, achieving high instruction throughput.

The instruction format defines the layout of bits in an instruction, including the opcode and operand address fields. Based on the number of addresses, CPUs are classified as follows:

1. Three-Address Instructions:

• Format: OP A, B, C →
• Program for :

ADD R1, A, B ; R1 = A + B
ADD R2, C, D ; R2 = C + D
MUL X, R1, R2 ; X = R1 * R2

• Advantage: Short programs. Disadvantage: Long instructions.

2. Two-Address Instructions:

• Format: OP A, B →

MOV R1, A ; R1 = A
ADD R1, B ; R1 = A + B
MOV R2, C ; R2 = C
ADD R2, D ; R2 = C + D
MUL R1, R2 ; R1 = R1 * R2
MOV X, R1 ; X = R1

3. One-Address Instructions:

• Use an implied accumulator (AC).

LOAD A ; AC = A
ADD B ; AC = A + B
STORE T ; T = AC
LOAD C ; AC = C
ADD D ; AC = C + D
MUL T ; AC = AC * T
STORE X ; X = AC

4. Zero-Address Instructions (Stack):

• Use a stack; operands are implied at top of stack.

PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X

Trade-off: More addresses → shorter programs but longer instructions; fewer addresses → longer programs but compact instructions.

The Processor Status Word (PSW), also called the status register or condition code register, is a register that holds the current status of the processor, primarily the condition flags set by ALU operations.

Purpose:

• Records the outcome of arithmetic and logic operations
• Used by conditional branch instructions to make decisions
• May also store interrupt masks, mode bits, and priority levels

Common Status Flags:

1. Carry Flag (C):

• Set to if there is a carry-out from the most significant bit (MSB) during addition, or a borrow during subtraction.
• Used in multi-word and unsigned arithmetic.

2. Sign Flag (S):

• Equals the MSB of the result.
• indicates a negative result (in signed representation); indicates positive.

3. Zero Flag (Z):

• Set to when the result of an operation is zero; otherwise .
• Used for equality comparisons.

4. Overflow Flag (V):

• Set to when a signed arithmetic overflow occurs (result exceeds the representable range).
• Detected when carry into the MSB differs from carry out of the MSB:
  

Usage Example:
After a SUBTRACT operation, a Branch if Zero (BZ) instruction tests the Z flag to detect equality of two numbers.

Program control instructions alter the normal sequential flow of program execution by modifying the value in the Program Counter (PC).

Types of Program Control Instructions:

• Branch / Jump (BR, JMP): Unconditionally transfer control to a target address.
• Conditional Branch (BZ, BNZ, BC, etc.): Transfer control only if a condition (based on status flags) is met.
• Call and Return (CALL, RET): Used for subroutine handling; save/restore the return address.
• Compare (CMP) and Test (TST): Perform subtraction/AND without storing results, only to update flags.
• Skip: Conditionally skip the next instruction.

Conditional Branch Instructions and Flags:

Working:

• A compare instruction subtracts operands and updates flags.
• The following conditional branch tests the relevant flag.
• If the condition holds, PC is loaded with the branch target; otherwise, execution continues sequentially.

This mechanism implements decision-making, loops, and comparisons in programs.

An interrupt is a signal that temporarily suspends the normal execution of a program so that the CPU can service an urgent event, after which it resumes the interrupted program.

Interrupt Handling Steps:

• Save the current program state (PC and PSW) on the stack.
• Transfer control to the Interrupt Service Routine (ISR).
• Execute the ISR.
• Restore the saved state and resume execution.

Types of Interrupts:

1. External Interrupts:

• Originate from external devices (I/O, timer, power failure).
• Example: A keyboard signals that a key has been pressed.

2. Internal Interrupts (Traps / Exceptions):

• Arise from illegal or exceptional conditions during instruction execution.
• Examples: division by zero, arithmetic overflow, invalid opcode, stack overflow.
• These are synchronous — they occur at a predictable point.

3. Software Interrupts:

• Generated by executing a special instruction (e.g., INT n or a system call/SVC).
• Used to request operating system services.

Comparison:

Maskable vs Non-Maskable:

• Maskable interrupts can be disabled by the CPU.
• Non-maskable interrupts (NMI) cannot be ignored (e.g., power failure).

Data transfer schemes define how data is moved between the CPU/memory and I/O devices.

1. Programmed I/O:

• The CPU is fully responsible for the data transfer.
• The CPU continuously polls (checks) the status flag of the device.
• When the device is ready, the CPU transfers the data.
• Disadvantage: CPU wastes time in the polling (busy-wait) loop; very inefficient.

2. Interrupt-Driven I/O:

• The device interrupts the CPU when it is ready for data transfer.
• The CPU need not poll; it performs other tasks meanwhile.
• On interrupt, the CPU suspends its work, runs the ISR to transfer data, then resumes.
• Advantage: Better CPU utilization than programmed I/O.
• Disadvantage: CPU still handles each word transfer, incurring overhead.

3. Direct Memory Access (DMA):

• A dedicated DMA controller transfers data directly between memory and the I/O device without CPU involvement for each word.
• Steps:
  • CPU initializes the DMA controller (address, count, direction).
  • DMA requests the system bus (Bus Request, BR).
  • CPU grants the bus (Bus Grant, BG) and enters a hold state.
  • DMA transfers the block of data.
  • DMA interrupts the CPU when done.
• Cycle Stealing: DMA takes bus cycles when CPU is not using the bus.
• Advantage: High-speed bulk transfer; ideal for disk and network devices.

Comparison:

Direct Memory Access (DMA) is a data transfer technique that allows I/O devices to exchange data directly with main memory without continuous CPU intervention, greatly improving transfer speed for large data blocks.

Need for DMA:

• Programmed and interrupt-driven I/O involve the CPU in every word transfer, causing overhead for high-speed devices like disks.

DMA Controller Registers:

• Address Register: Holds the memory address for the next transfer.
• Word Count Register: Number of words to transfer.
• Control Register: Specifies mode and direction of transfer.

Working Steps:

1. Initialization: CPU sends the starting address, word count, and read/write control to the DMA controller.
2. Bus Request (BR): DMA requests control of the system bus.
3. Bus Grant (BG): CPU relinquishes the bus and enters a hold state; the DMA becomes bus master.
4. Transfer: DMA transfers data directly between the device and memory, incrementing the address and decrementing the count.
5. Completion: When the count reaches zero, DMA sends an interrupt to the CPU.

Transfer Modes:

1. Burst (Block) Transfer:

• DMA transfers an entire block of data in one continuous operation while holding the bus.
• CPU is blocked during the transfer.
• Fast, used for high-speed devices.

2. Cycle Stealing:

• DMA transfers one word at a time, stealing a single bus cycle from the CPU whenever the bus is free.
• CPU execution slows slightly but is not completely blocked.
• Good balance between transfer speed and CPU availability.

Advantages:

• Frees CPU for other computation
• High throughput for bulk data

Disadvantage:

• Additional hardware (DMA controller) and bus contention.

Both subroutine calls and interrupts transfer control away from the main program and later return, but they differ in origin and mechanism.

Comparison:

Return Address Handling:

Subroutine Call:

• On CALL, the current PC (return address) is pushed onto the stack:
  
• The PC is loaded with the subroutine's start address.
• On RET, the return address is popped back:
  

Interrupt:

• On interrupt acceptance, both the PC and PSW are pushed onto the stack (so the exact processor state is preserved).
• The PC is loaded from the interrupt vector corresponding to the interrupt source.
• On RETI, both PSW and PC are restored to resume the interrupted program exactly.

Key Difference: Interrupts save the full processor status (including flags) because they may occur at any point, whereas a subroutine call typically saves only the return address.

Priority Interrupt: When multiple devices request interrupts simultaneously, a priority interrupt system determines which device is serviced first, based on the relative importance (priority) of each device.

Need:

• High-speed and critical devices should be serviced before slower or less critical ones.
• Prevents conflicts when several interrupts arrive together.

Methods of Establishing Priority:

• Software (Polling): CPU checks each device in priority order.
• Hardware (Daisy-Chaining, Parallel Priority): Faster hardware-based resolution.

Daisy-Chaining Priority:

All devices are connected in series to form a chain. The device closest to the CPU has the highest priority.

Working:

1. All devices share a common interrupt request line to the CPU.
2. When one or more devices raise an interrupt, the CPU responds with an interrupt acknowledge (INTACK) signal.
3. The acknowledge signal propagates down the chain from the highest-priority device.
4. Each device has a Priority In (PI) and Priority Out (PO) line:
   • If a device is not requesting an interrupt, it passes the acknowledge signal to the next device ().
   • If a device is requesting, it blocks the signal () and places its Vector Address (VAD) on the bus.
5. The CPU uses the vector address to branch to the correct ISR.

Advantages:

• Simple and inexpensive hardware.
• Easy to add devices.

Disadvantages:

• Devices far from the CPU have low priority and may face starvation.
• Propagation delay through the chain increases with the number of devices.

These three addressing modes differ in how and where the operand is located.

1. Immediate Addressing Mode:

• The operand is contained within the instruction itself.
• No memory reference needed to fetch the operand (beyond the instruction fetch).
• Example: ADD #5 → adds the constant 5.
• Use case: Initializing registers, using constants.

2. Direct (Absolute) Addressing Mode:

• The address field contains the effective address of the operand in memory.
• ; operand = .
• Requires one memory reference to get the operand.
• Example: LOAD 500 → loads content of memory location 500.
• Use case: Accessing fixed memory variables.

3. Indirect Addressing Mode:

• The address field points to a memory location that holds the address of the operand.
• ; operand = .
• Requires two memory references.
• Example: LOAD @500 → 500 holds the address of the actual operand.
• Use case: Pointers, dynamic data structures.

Comparison Table:

Summary: Immediate is fastest but inflexible; direct offers straightforward access; indirect provides flexibility (pointers) at the cost of extra memory access.

The CPU is the core unit that fetches, decodes, and executes instructions. It contains the ALU, control unit, and several special-purpose registers.

Key Registers:

• Program Counter (PC): Holds the address of the next instruction to be fetched.
• Instruction Register (IR): Holds the current instruction being decoded/executed.
• Memory Address Register (MAR): Holds the memory address to be accessed (read/write).
• Memory Data Register (MDR / MBR): Holds the data read from or written to memory.
• Accumulator (AC): Holds intermediate ALU results.

Instruction Cycle Phases:

1. Fetch Phase:

• Address in PC is copied to MAR:
  
• Instruction is read from memory into MDR:
  
• Instruction transferred to IR:
  
• PC incremented to point to next instruction:
  

2. Decode Phase:

• The control unit decodes the opcode in the IR to determine the operation and addressing mode.

3. Fetch Operand (if required):

• The effective address is computed and the operand is fetched from memory into MDR.

4. Execute Phase:

• The ALU performs the required operation; the result is stored in a register or memory.

5. Check Interrupt:

• If an interrupt is pending, the CPU services it before fetching the next instruction.

This cycle repeats continuously, forming the fetch-decode-execute loop that drives program execution.

Autoincrement and autodecrement addressing modes are variants of the register indirect mode where the content of the register (which holds an address) is automatically modified after or before it is used.

1. Autoincrement Mode:

• The register holds the operand's address.
• After the operand is accessed, the register is incremented (typically by the operand size).
• Notation: (R)+
• Operation:
  
  where is the data element size.

2. Autodecrement Mode:

• The register is decremented first, and then used as the operand's address.
• Notation: -(R)
• Operation:
  

Usefulness in Array Processing:

• Arrays are stored in consecutive memory locations.
• Using autoincrement, a single register can point to array elements, and after each access it automatically advances to the next element.
• This eliminates explicit index update instructions inside loops, making array traversal efficient.
• Example (summing an array):

LOOP: ADD (R1)+ ; access element, then R1++
...

Usefulness in Stack Operations:

• A stack pointer naturally increments on push and decrements on pop (or vice versa).
• PUSH can use autodecrement, POP can use autoincrement (in a stack growing toward lower addresses):
  
  

Conclusion: These modes reduce instruction count and simplify sequential data access, improving performance in loops and stack management.

The control unit generates the control signals that coordinate the operation of the CPU. It can be implemented in two ways.

1. Hardwired Control Unit:

• Control signals are generated by fixed combinational logic circuits (gates, flip-flops, decoders).
• The design is based directly on the required sequence of operations.
• Advantages: Very fast; suitable for simple instruction sets.
• Disadvantages: Complex and difficult to design/modify; not flexible.

2. Microprogrammed Control Unit:

• Control signals are generated by microinstructions stored in a special control memory (ROM).
• Each machine instruction corresponds to a sequence of microinstructions (a microprogram).
• Advantages: Flexible, easy to modify, supports complex instructions.
• Disadvantages: Slower due to control-memory access.

Comparison Table:

Relationship with RISC and CISC:

• RISC typically uses a hardwired control unit because its instructions are few, simple, and fixed-length. Hardwired control provides the speed needed for single-cycle execution and efficient pipelining.

• CISC typically uses a microprogrammed control unit because its instruction set is large and complex with variable-length instructions and many addressing modes. Microprogramming makes it feasible to implement and modify these complex instructions.

Conclusion: The choice reflects each philosophy — RISC favors speed and simplicity (hardwired), while CISC favors flexibility and rich functionality (microprogrammed).