Unit 2: Computer Organization - Subjective Questions

An instruction code is a group of bits that instructs the computer to perform a specific operation. It is usually divided into parts, each having its own particular interpretation.

Two basic parts:

• Operation Code (Opcode): A group of bits that defines the operation to be performed such as add, subtract, complement, or shift. For a basic computer with distinct operations, the opcode requires bits. In the basic computer, the opcode is 3 bits (bits 12–14), allowing operations.

• Address: A group of bits that specifies the location (address) of the operand in memory on which the operation is performed. In the basic computer, the address field is 12 bits (bits 0–11), allowing addressing of memory words.

Additional field:

• Mode bit (I): Bit 15 specifies the addressing mode (direct = 0 or indirect = 1).

The stored program concept requires instruction codes and operands to be stored in memory; the control unit reads and interprets these codes to execute the program.

The mode bit (I) at position 15 of an instruction determines the addressing mode used to access the operand.

Direct Addressing (I = 0):

• The address field of the instruction directly points to the memory location of the operand.
• One memory access is needed to fetch the operand.
• Example: LDA 500 — The operand is located at address 500.

Instruction: 0 | opcode | 457
Memory[457] = operand (used directly)

Indirect Addressing (I = 1):

• The address field points to a memory location that holds the effective address of the operand.
• Two memory accesses are needed: one to get the effective address, another to get the operand.
• Example: LDA 500 I — Memory[500] contains the actual address of the operand.

Instruction: 1 | opcode | 300
Memory[300] = 1350 (effective address)
Memory[1350] = operand

Key points:

• Direct addressing is faster (one access).
• Indirect addressing enables pointers and dynamic addressing but is slower.
• The effective address is the address of the operand actually used in a memory-reference instruction.

The basic computer has eight registers, a memory unit, and a control unit. The registers and their functions are:

Descriptions:

• AR (12-bit): Since memory has words, the address register needs 12 bits to point to any location.
• PC (12-bit): Holds the address of the next instruction; incremented after each fetch.
• DR (16-bit): Holds the operand read from memory.
• AC (16-bit): The main working register for arithmetic and logic operations.
• IR (16-bit): Holds the instruction currently being executed.
• TR (16-bit): Used for temporary storage during processing.
• INPR / OUTR (8-bit): Handle 8-bit ASCII characters for I/O.

A common bus system provides a single set of pathways to transfer data between the various registers and memory efficiently, avoiding a large number of dedicated wires.

Structure:

• The outputs of the seven registers (AR, PC, DR, AC, IR, TR) and memory are connected to a common bus through three-state buffers (gates).
• The bus is 16 bits wide.

Register selection:

• Selection variables (3 bits) determine which register/memory places its content on the bus at any time.
• selections are possible (one for memory, others for registers).

Control of transfers:

• Each register has LD (load), INR (increment), CLR (clear) control inputs.
• When a register's LD is enabled, it receives data from the bus during the clock pulse.
• Example micro-operation: DR ← AC places AC on bus (selection 100) and enables LD of DR.

Advantages: Reduces wiring complexity and cost, though only one transfer per clock on the bus is allowed.

The basic computer has three instruction code formats, distinguished by the opcode value.

1. Memory-Reference Instructions (MRI):

• Format: I (1 bit) | Opcode (3 bits, 000–110) | Address (12 bits)
• The opcode ranges from 000 to 110 (7 operations).
• Bit 15 (I) specifies direct/indirect addressing.
• Examples: AND, ADD, LDA, STA, BUN, BSA, ISZ.

2. Register-Reference Instructions:

• Format: 0 | 111 | Register operation (12 bits)
• Opcode = 111 with I = 0.
• The 12 bits specify the register operation.
• Examples: CLA, CLE, CMA, CME, CIR, CIL, INC, SPA, SNA, SZA, SZE, HLT.

3. Input-Output Instructions:

• Format: 1 | 111 | I/O operation (12 bits)
• Opcode = 111 with I = 1.
• Examples: INP, OUT, SKI, SKO, ION, IOF.

Distinguishing logic:

• If opcode ≠ 111 → Memory-reference.
• If opcode = 111 and I = 0 → Register-reference.
• If opcode = 111 and I = 1 → Input-output.

This design allows a 3-bit opcode to support far more than 8 operations.

The control unit generates timing and control signals to coordinate operations. It can be implemented in two ways.

Hardwired Control:

• Control signals are generated by combinational logic based on the instruction decoder, timing signals, and flags.
• Optimized for speed.

Microprogrammed Control:

• Each machine instruction is broken into a sequence of microinstructions stored in control memory.
• Provides systematic design and easy maintenance at the cost of speed.

The timing and control unit governs all operations of the computer using a master clock and control logic.

Components:

• Master Clock Generator: Provides clock pulses that synchronize all registers. A pulse does not change register state unless the register is enabled by a control signal.

• Sequence Counter (SC): A 4-bit counter that can count from 0 to 15. Its output feeds a 4×16 decoder producing timing signals .

• Timing Signals (): Only one timing signal is active at a time, in sequence, controlling the step-by-step execution of micro-operations.

Working:

• Initially SC = 0, so is active.
• On each clock pulse SC increments:
• SC can be cleared to 0 synchronously using the CLR input, restarting the timing sequence for the next instruction.

Example (fetch phase):

• : AR ← PC
• : IR ← M[AR], PC ← PC + 1
• : D0..D7 ← decode IR(12-14), AR ← IR(0-11), I ← IR(15)

Types of control organization: hardwired and microprogrammed. The basic computer uses a hardwired approach where control signals are Boolean functions of , , and the instruction bits.

An instruction cycle is the sequence of steps required to fetch and execute a single instruction. Program execution consists of repeating this cycle until a HALT is reached.

Four Phases:

1. Fetch Instruction: The instruction is read from memory into the instruction register.

   • : AR ← PC
   • : IR ← M[AR], PC ← PC + 1

2. Decode Instruction: The opcode is interpreted and the effective address determined.

   • : D0..D7 ← decode IR(12-14), AR ← IR(0-11), I ← IR(15)

3. Read Effective Address: If it is a memory-reference instruction, fetch operand address (handling indirect addressing).

   • (I = 1, indirect): AR ← M[AR]

4. Execute Instruction: Perform the operation specified by the opcode.

Flow after decoding at :

• If → register-reference or I/O instruction.
• If and I = 1 → indirect address fetch.
• If and I = 0 → direct memory reference.

After execution, SC is cleared to 0 to restart the cycle for the next instruction. This continuous fetch–decode–execute loop drives program execution.

Register-reference instructions are recognized when the opcode = 111 () and the mode bit I = 0. They operate mainly on the accumulator (AC) and flip-flops without referencing memory.

They are executed at timing signal and each is identified by a specific bit ( to ) in the instruction.

Common control function:

Micro-operations (examples):

• CLA (Clear AC):
• CLE (Clear E):
• CMA (Complement AC):
• CME (Complement E):
• CIR (Circulate Right):
• CIL (Circulate Left):
• INC (Increment AC):
• SPA (Skip if Positive):
• SNA (Skip if Negative):
• HLT (Halt): (stops the computer)

These instructions execute in a single timing step, making them very fast.

Memory-reference instructions (MRI) access memory to fetch or store operands. They are decoded when the opcode is 000–110 (–). Execution begins at timing signal after the effective address is computed.

The seven MRIs: AND, ADD, LDA, STA, BUN, BSA, ISZ.

ADD instruction (): Adds the memory operand to AC.

• (read operand into DR)

Here is the carry flip-flop that stores the output carry; SC is cleared to end the cycle.

STA instruction (): Stores the content of AC into memory.

Storing requires only one timing step because no operand read is needed.

General approach for MRI:

1. At , transfer operand from memory to DR (if needed).
2. At (or ), perform the operation and clear SC.

The effective address in AR was already computed during the fetch/indirect phase (/).

Input-Output configuration:

• Input Register (INPR): 8-bit register holding the character entered from the input device (e.g., keyboard).
• Output Register (OUTR): 8-bit register holding the character to be sent to the output device (e.g., printer).
• FGI (Input Flag): 1-bit flip-flop set to 1 when a new character is in INPR, cleared after the CPU reads it.
• FGO (Output Flag): 1-bit flip-flop set to 1 when the output device is ready to receive a character.

I/O Instructions (opcode = 111, I = 1, executed at , control ):

• INP (Input, ): — transfers input character to AC and clears input flag.
• OUT (Output, ): — transfers character from AC to output register.
• SKI (Skip on input flag, ): if then — skips next instruction if input ready.
• SKO (Skip on output flag, ): if then — skips next instruction if output ready.
• ION / IOF: enable / disable the interrupt facility.

Programmed I/O: The CPU repeatedly checks flags (using SKI/SKO) before transferring data — this is busy waiting, which wastes CPU time.

An interrupt allows an I/O device to signal the CPU asynchronously, avoiding wasteful busy-waiting of programmed I/O.

Interrupt mechanism:

• An interrupt enable flip-flop (IEN) must be set (by the ION instruction) to allow interrupts.
• The interrupt flip-flop R is set when a device flag (FGI or FGO) becomes 1 while IEN = 1.

Interrupt condition:

The CPU checks for interrupts only between instructions (after the current instruction completes).

Interrupt Cycle micro-operations (when R = 1):

• (save return address in TR, prepare to store at address 0)
• (store return address, branch to location 0)

Explanation:

• The return address (PC) is saved in memory location 0.
• Control branches to the interrupt service routine located at address 1.
• IEN is cleared to disable further interrupts during servicing.
• After servicing, a BUN 0 I (indirect branch) returns control to the interrupted program.

This makes I/O efficient because the CPU works on other tasks until interrupted.

These are three techniques for transferring data between the CPU/memory and I/O devices.

1. Programmed I/O:

• CPU executes SKI/SKO to poll device flags.
• Simple but wastes CPU time in busy waiting.

2. Interrupt-Driven I/O:

• Device raises an interrupt when ready; CPU services it via an ISR.
• CPU can do useful work in between, improving utilization.

3. Direct Memory Access (DMA):

• A DMA controller takes over the bus (cycle stealing) and transfers data directly between memory and the device.
• CPU is freed except at start and end of transfer, ideal for large data blocks.

The Little Man Computer (LMC) is a simple instructional model of a computer, created to teach the basic principles of the von Neumann architecture and machine-level operation. It uses simulation software to visualize how a CPU executes programs.

Concept: Imagine a little man inside a mailroom who fetches, decodes, and executes instructions manually.

Main Components:

• Mailboxes (Memory): 100 memory locations numbered 00 to 99, each holding a 3-digit instruction or data value.
• Accumulator (Calculator): A register that holds values and performs arithmetic (add/subtract).
• Program Counter: Holds the address (00–99) of the next instruction to execute; normally incremented by 1.
• Instruction Register / Decoder: Interprets the current instruction's opcode.
• Input Basket (Inbox): Where input data is placed.
• Output Basket (Outbox): Where results are displayed.

Instruction format: Each instruction is a 3-digit number — the first digit is the opcode and the last two digits are the operand/address.

Working: The little man repeatedly (1) reads the PC, (2) fetches the instruction from the mailbox, (3) increments the PC, (4) decodes and executes the instruction — mirroring the real fetch-decode-execute cycle.

LMC helps beginners understand memory addressing, the instruction cycle, and assembly programming in a simplified manner.

The Little Man Computer (LMC) uses a small instruction set where each instruction is a 3-digit number: the first digit is the opcode and the remaining two digits are the operand address (xx).

Explanation of key groups:

• Data movement: LDA, STA move data between AC and memory.
• Arithmetic: ADD, SUB operate on AC.
• Branching: BRA, BRZ, BRP control program flow (loops, decisions).
• I/O: INP (901) and OUT (902) share opcode 9 with different operands.
• Control: HLT (000) stops the little man.

DAT is not executed; it is used to declare variables or constants in memory.

Below is an LMC assembly program that reads two numbers, adds them, and outputs the sum.

    INP         // Input first number into AC
    STA NUM1    // Store it in NUM1
    INP         // Input second number into AC
    ADD NUM1    // AC = second + NUM1
    OUT         // Output the sum
    HLT         // Stop execution

NUM1 DAT 0 // Storage for first number

Step-by-step explanation:

• INP (901): First number entered from the inbox is loaded into the accumulator (AC).
• STA NUM1 (3xx): The value in AC is stored into the memory location labeled NUM1.
• INP (901): The second number is loaded into AC (overwriting the first).
• ADD NUM1 (1xx): The value in NUM1 (first number) is added to AC, so AC now holds the sum.
• OUT (902): The sum in AC is sent to the outbox and displayed.
• HLT (000): Execution stops.
• NUM1 DAT 0: Reserves a mailbox initialized to 0 to store the first number.

Trace example: Input 7 and 5 → AC = 7 → NUM1 = 7 → AC = 5 → AC = 5 + 7 = 12 → Output = 12.

The fetch phase reads the next instruction from memory into the instruction register and prepares to decode it. It occurs during timing signals , , and .

Micro-operations:

• • The program counter holds the address of the next instruction. This address is transferred to the address register so memory can be accessed. (PC output on bus, AR loaded.)

• • The instruction at the address in AR is read from memory into the instruction register. Simultaneously, PC is incremented so it points to the following instruction.

• • The opcode (bits 12–14) is decoded to identify the operation. The address field (bits 0–11) is moved into AR (potential effective address). The mode bit (bit 15) is copied to the I flip-flop.

Justification:

• Using AR keeps a single memory-address source for the bus.
• Incrementing PC during fetch ensures sequential execution unless a branch changes it.
• Decoding at lets the control unit choose the correct execution path (memory-reference, register-reference, or I/O) at .

Both BSA and ISZ are memory-reference instructions that support subroutine calls and loop control.

BSA – Branch and Save return address ():
Used to call a subroutine. It saves the return address at the subroutine's first location and branches to the next location.

Explanation: The return address (current PC) is stored at address AR (start of the subroutine). AR is incremented, and PC is set to AR so execution continues at the instruction after the saved return address. The subroutine returns using an indirect BUN to the saved address.

ISZ – Increment and Skip if Zero ():
Used to implement counters/loops. It increments a memory word and skips the next instruction if the result is zero.

Use: Store a negative count in memory; each iteration ISZ increments it, and when it reaches 0 the loop-exit path is taken via the skip.

Together, BSA enables subroutines and ISZ enables loop counting.

After the fetch phase, at the control unit must decide which of the three instruction categories to execute. It uses the decoder output and the mode bit I.

Decision logic at :

• The decoder gives outputs to from the opcode bits (12–14).
• distinguishes memory-reference (opcode 000–110) from the special group (opcode 111).

Cases:

1. (Memory-Reference Instruction):

   • If I = 1 (indirect): AR ← M[AR] — fetch effective address.
   • If I = 0 (direct): nothing extra; AR already holds the address.
   • Micro-op: and nothing.

2. and I = 0 (Register-Reference Instruction):

   • Execute register operation directly.
   • Control function .

3. and I = 1 (Input-Output Instruction):

   • Execute I/O operation.
   • Control function .

Flowchart summary:

    (T3, decode done)
          |
    Is D7 = 0 ?
     /        \
   Yes         No (D7 = 1)
    |            |

Memory-Ref Is I = 0 ?
Is I = 1? / \
/ \ Yes No
Yes No Register- I/O
indirect direct Reference Instruction
AR←M[AR] (nothing)

This branching lets a single 3-bit opcode support memory, register, and I/O operations, and the control unit generates the correct micro-operations for the next timing steps.

The Little Man Computer (LMC) is a teaching abstraction of the von Neumann basic computer. Both share the stored-program concept but differ in complexity.

Similarities:

• Both follow the stored-program (von Neumann) architecture — instructions and data reside in the same memory.
• Both use a fetch–decode–execute instruction cycle.
• Both have a program counter, an accumulator, memory, and I/O.
• Instructions consist of an opcode + operand/address.

Differences:

Conclusion: LMC simplifies away binary encoding, multiple registers, addressing modes, and interrupts to make the core fetch-execute principle intuitive, while the basic computer models these realistic hardware details.