Unit 3: Central Processing Unit

The Central Processing Unit (CPU) is the component that fetches, decodes and executes instructions. It is built from three cooperating parts — a register set for operand storage, an arithmetic logic unit (ALU) for computation, and a control unit that sequences micro-operations. Everything below describes how operands reach the ALU, how instructions are encoded, and how the flow of control is managed.

• Datapath: the registers and ALU together, connected by internal buses that route operands into the ALU and results back to registers.
• Register–ALU–register cycle: operands are read from registers, an operation is performed, and the result is written back — often in a single clock.
• Instruction cycle: fetch (read instruction using PC), decode (interpret opcode), execute (perform the micro-operations).
• Word length: the natural operand width (e.g., 16, 32, 64 bits) that fixes register size and bus width.

II. General Register Organization

Operands held in a bank of CPU registers rather than in memory.

A. Register bank and common bus

A set of general-purpose registers is connected to the ALU through multiplexers and a common bus so any register can be a source or destination.

• Structure: n registers feed two multiplexers (MUX A, MUX B) selecting the ALU inputs; the ALU output returns via a decoder to a selected register.
• Control word: a field bundle SELA | SELB | SELD | OPR chooses source A, source B, destination D, and the operation.
• Example micro-operation: R1 ← R2 + R3 sets SELA=R2, SELB=R3, SELD=R1, OPR=ADD — executed in one clock.
• Advantage: avoids repeated memory access by keeping active operands on-chip, reducing effective instruction time.

III. Stack Organization

A LIFO storage area for temporary data, addresses and return links.

A. Register stack and memory stack

The stack can be a fixed set of registers or a region of memory addressed by a stack pointer.

• Register stack: finite depth with FULL and EMPTY flags; SP points to the top word.
  • Push: SP ← SP + 1; M[SP] ← DR (increment then store).
  • Pop: DR ← M[SP]; SP ← SP − 1 (read then decrement).
• Memory stack: SP holds an address inside main memory; grows downward in most designs (SP ← SP − 1 on push).

B. Reverse Polish Notation (postfix)

Stacks evaluate arithmetic without parentheses using postfix ordering.

• Rule: operands are pushed; an operator pops the top two, computes, and pushes the result.
• Worked example: (3 + 4) × 5 becomes 3 4 + 5 × → push 3, push 4, +→7, push 5, ×→35.

IV. Addressing Modes

The rules by which the effective address (EA) of an operand is derived from the instruction.

A. The addressing modes

Each mode trades flexibility against instruction size and access time.

• Implied: operand is fixed by the opcode: e.g., CLA clears the accumulator; no address field.
• Immediate: operand is in the instruction itself: MOV R1, #5.
• Register: operand is in a register: EA = register; ADD R1, R2.
• Register indirect: register holds the address: EA = (R1).
• Autoincrement / Autodecrement: register indirect with automatic update, used to step through arrays: EA = (R1); R1 ← R1 + 1.
• Direct: address field is the EA: LOAD 500 → operand at M[500].
• Indirect: address field points to a memory word holding the EA: EA = M[address field].
• Relative: EA = PC + address field, giving position-independent branches.
• Indexed: EA = XR + address field, where XR is an index register — ideal for arrays.
• Base register: EA = BR + address field, used for relocation of program segments.

V. Reduced Instruction Set Computer

A design philosophy favouring a small set of simple, fixed-length instructions.

A. Characteristics

RISC keeps hardware simple so that most instructions complete in one cycle.

• Uniform format: fixed instruction length eases decoding and pipelining.
• Load/store architecture: only LOAD and STORE touch memory; all arithmetic is register-to-register.
• Large register file: many registers reduce memory traffic; overlapped register windows speed procedure calls.
• Few addressing modes: typically register and displacement only, simplifying the control unit.
• Hardwired control: control signals from combinational logic, not microcode, allowing higher clock rates.
• Example families: ARM, MIPS, SPARC.

VI. Complex Instruction Set Computer

A philosophy providing many powerful, variable-length instructions close to high-level statements.

A. Characteristics

CISC reduces program size and eases compilation by doing more work per instruction.

• Variable-length instructions: opcode plus differing operand fields; compact code.
• Memory-to-memory operations: operands may reside directly in memory, so a single instruction can add two memory words.
• Many addressing modes: rich set (indexed, indirect, relative) increases flexibility.
• Microprogrammed control: microcode interprets complex instructions, at the cost of slower per-instruction timing.
• Example families: Intel x86, VAX.

B. RISC versus CISC contrast

The two philosophies optimise different quantities in the performance equation time = instructions × cycles/instruction × cycle-time.

1. RISC: more instructions per program, but low cycles-per-instruction and short cycle time; relies on optimising compilers and pipelines.
2. CISC: fewer instructions per program, but higher cycles-per-instruction and longer cycle time; relies on microcode.

VII. Instruction Formats

The layout of bits within an instruction, dividing opcode from operand specifiers.

A. Fields and organization by operand count

The number of address fields defines the CPU organization.

• Fields: an opcode field, one or more address/register fields, and a mode field.
• Three-address: ADD R1, R2, R3 → R1 ← R2 + R3; typical of general-register machines; short programs, long instructions.
• Two-address: ADD R1, R2 → R1 ← R1 + R2; one operand doubles as destination.
• One-address: ADD X → AC ← AC + M[X]; uses an implied accumulator.
• Zero-address: ADD; operands are implied on a stack — used in stack machines.
• Illustration: to compute X = (A+B)×(C+D) the count of instructions rises as the address count falls, trading code size for hardware simplicity.

VIII. Data Transfer Schemes

The methods by which the CPU exchanges data with I/O devices, coordinated against timing differences.

A. Programmed and interrupt-driven transfer

These schemes involve the CPU directly in each transfer.

• Programmed I/O: CPU polls a status flag in a loop and moves each data word itself; simple but wastes CPU cycles busy-waiting.
• Interrupt-initiated I/O: the device raises an interrupt when ready; CPU services it and returns, so it need not poll.

B. Direct Memory Access (DMA)

DMA removes the CPU from the data-moving loop for high-speed devices.

• Principle: a DMA controller takes control of the buses to transfer blocks directly between device and memory.
• Bus handshake: device asserts BR (bus request); CPU replies BG (bus grant) and floats its buses (cycle stealing or burst mode).
• Registers: address register (memory location), word-count register (block size), control register (direction).
• Benefit: the CPU is interrupted only once per block, not once per word.

IX. Program Control and Interrupts

Instructions and mechanisms that alter the sequential flow of execution.

A. Program control instructions

These change the program counter conditionally or unconditionally.

• Branch/Jump: load a new address into PC: BR ADR, or conditional BZ, BNZ.
• Compare and test: set status bits by subtraction/AND without storing the result, so a following branch can act on them.
• Subroutine call/return: CALL saves the return address (often on the stack) and loads the subroutine address; RET pops it back.
• Conditional branch anchor: if (A ≥ B) goto L compiles to CMP A,B then BGE L.

B. Interrupts

An interrupt suspends the current program to service an urgent condition, preserving state for resumption.

• Types: external (I/O, timer), internal or trap (overflow, divide-by-zero), and software (INT n).
• Service sequence: finish current instruction → save PC and PSW → load the interrupt-service address → execute handler → restore state on return.
• Priority: higher-priority sources preempt lower ones; a priority encoder or daisy chain resolves simultaneous requests.
• Vectored vs non-vectored: the device supplies the handler address directly (vectored) or the CPU branches to a fixed location (non-vectored).

X. Processor Status Word

A dedicated register holding the condition flags and mode bits describing CPU state.

A. Condition flags and mode bits

The PSW (or program status word) is saved and restored across interrupts and calls.

• Carry (C): set when an operation produces a carry-out of the most-significant bit.
• Sign (S): copies the MSB of the result, indicating a negative value in signed arithmetic.
• Zero (Z): set when the result is all zeros.
• Overflow (V): set when a signed result exceeds the representable range.
• Mode bits: an interrupt-enable flag and a supervisor/user bit that governs privileged operation.
• Role in control: conditional branches test C, S, Z and V; saving the PSW on interrupt lets the interrupted program resume with its flags intact.