Unit 2: Computer Organization

This unit builds on the Basic Computer of Mano's design — a hypothetical 16-bit machine with a single accumulator, one memory-referencing addressing scheme, and a hardwired control unit. It is the reference model against which registers, buses, instruction formats and control timing are studied.

• Word size: 16 bits; memory holds 4096 words (12-bit address), so a word doubles as either an instruction or an operand.
• Single accumulator (AC): all arithmetic and logic funnels through one register; the second operand comes from memory.
• Von Neumann storage: instructions and data share the same memory, fetched one word at a time.
• Synchronous, hardwired control: a master clock and a sequence counter drive every micro-operation; there is no microprogram.

II. Instruction Codes

An instruction code is a group of bits telling the computer to perform a specific operation, split into an operation part and an address/mode part.

A. Format of an instruction code

• Opcode field: bits 12–14 (3 bits) select one of eight basic operations.
• Address field: bits 0–11 (12 bits) point to a memory word.
• Mode bit I: bit 15 selects addressing mode.

15  | 14 13 12 | 11 ................. 0
 I  |  Opcode  |     Address (12 bits)

B. Direct and indirect addressing

1. Direct (I = 0): the address field is the operand's effective address; one memory access reaches the data.
2. Indirect (I = 1): the address field points to a word that in turn holds the effective address; two accesses are needed.
   • Effective address (EA): the actual location used by the operation — computed at the start of execution.

C. Stored-program concept

• Instruction fetch: the control reads the word at the address in PC, treats its bits as an opcode + address.
• Program: a sequence of such coded words placed in successive memory locations.

III. Computer Registers

Registers hold information the CPU is actively using — addresses, data, instructions and counters — because memory alone is too slow to sequence operations.

A. The register set

• AC (16 bits): accumulator, the main processing register.
• DR (16 bits): data register, holds the operand read from memory.
• AR (12 bits): address register, holds the memory address currently accessed.
• PC (12 bits): program counter, holds the address of the next instruction.
• IR (16 bits): instruction register, holds the fetched instruction.
• TR (16 bits): temporary register for intermediate values.
• INPR / OUTR (8 bits): input and output registers for character I/O.

B. Program counter behaviour

• Increment: after fetch, PC ← PC + 1 so execution advances sequentially.
• Branch: a jump instruction loads a new address, e.g. PC ← AR.

C. Memory word register

• AR and PC width: 12 bits, matching the 4096-word address space.
• DR–memory link: DR ← M[AR] reads; M[AR] ← DR writes.

IV. Common Bus System

A single shared set of lines connects all registers and memory so that data transfers use one path rather than dedicated wires between every pair.

A. Structure of the bus

• 16 common lines: carry one register's contents at a time.
• Selection lines S2 S1 S0: a 3-bit code chooses which of seven registers or memory drives the bus.
• Multiplexed output: exactly one source is enabled per clock; destinations load via their own load-control (LD) signals.

B. Register transfer through the bus

• Two-register transfer: the source is placed on the bus, the destination clocked in one cycle, e.g. AR ← PC selects PC (010) and asserts AR's load.
• Memory read/write: memory attaches to the bus as source (read) and receives from it as destination (write).

C. Advantages and limitation

• Economy: fewer interconnections than a point-to-point scheme.
• Serialisation: only one transfer per clock, so the bus is a throughput bottleneck.

V. Computer Instructions

The Basic Computer has three instruction formats distinguished by the opcode and mode bit, giving 25 distinct operations from a 3-bit opcode.

A. Three instruction types

1. Memory-reference (opcode 000–110): references a memory operand; bit 15 sets direct/indirect. Seven operations: AND, ADD, LDA, STA, BUN, BSA, ISZ.
2. Register-reference (opcode 111, I = 0): operates on AC only; bits 0–11 specify the micro-operation, e.g. CLA (clear AC), CMA (complement), INC, SZA.
3. Input-output (opcode 111, I = 1): bits 0–11 select I/O actions such as INP, OUT, ION, IOF.

B. Sample memory-reference semantics

• ADD: AC ← AC + M[EA], carry to E.
• LDA: AC ← M[EA] (load).
• STA: M[EA] ← AC (store).
• BUN: PC ← EA (unconditional branch).
• ISZ: M[EA] ← M[EA]+1; if zero, PC ← PC+1 (skip on zero).

C. Instruction set completeness

• Data movement, arithmetic/logic, control: all three classes are present, so any computation can be programmed despite the small opcode field.

VI. Timing and Control

Control logic generates the sequence of signals that select buses, load registers and drive micro-operations, all synchronised to a clock.

A. Hardwired control components

• Sequence counter (SC): a 4-bit counter producing timing states.
• 3×8 decoder: converts SC output into timing signals T0…T7.
• Opcode decoder: converts IR opcode into signals D0…D7.
• Control logic gates: combine T, D, I and flag bits into the actual control lines.

B. Timing signals

• Sequential activation: T0 active first, then T1, T2… one per clock edge.
• SC clear: SC ← 0 at the end of an instruction returns to T0.

T0: AR ← PC
T1: IR ← M[AR], PC ← PC + 1
T2: D0..D7 ← decode IR(12-14), AR ← IR(0-11), I ← IR(15)

C. Hardwired versus microprogrammed

1. Hardwired (used here): fast, fixed logic; hard to modify.
2. Microprogrammed (contrast): control words in a control memory; flexible but slower.

VII. Instruction Cycle

Instruction execution repeats a fixed cycle of phases until a HALT, tying together fetch, decode and execute.

A. Phases of the cycle

• Fetch: T0–T1 bring the instruction into IR and increment PC.
• Decode: T2 identifies opcode, address and mode.
• Effective-address computation: for indirect (I = 1, memory-reference) AR ← M[AR] at T3.
• Execute: T4 onward performs the operation, then SC ← 0.

B. Register vs memory-reference paths

1. Register/I-O (D7 = 1): decoded at T3, executed immediately without a memory operand.
2. Memory-reference (D7 = 0): T3 resolves EA, T4–T6 fetch operand and execute.

C. Worked micro-operation: ADD (direct)

D0 T4: DR ← M[AR]
D0 T5: AC ← AC + DR, E ← carry
D0 T6: SC ← 0        ; cycle ends, return to fetch

VIII. Input-Output and Interrupt

I/O moves characters between the CPU and external devices, and interrupts let devices signal readiness without the CPU polling continuously.

A. Input–output configuration

• INPR: receives an 8-bit character from the keyboard; FGI flag set when full.
• OUTR: holds a character for the printer; FGO flag set when ready.
• Program-controlled transfer: INP executes AC(0-7) ← INPR, FGI ← 0; OUT executes OUTR ← AC(0-7), FGO ← 0.

B. Interrupt mechanism

• IEN flag: interrupt enable, set by ION, cleared by IOF.
• R flip-flop: set when IEN·(FGI + FGO) is true, forcing an interrupt cycle.
• Interrupt cycle actions:

RT0: AR ← 0, TR ← PC
RT1: M[AR] ← TR, PC ← 0
RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0

• Return address: stored at location 0; the service routine begins at location 1.

C. Polling versus interrupt

1. Programmed I/O (polling): CPU repeatedly tests FGI/FGO, wasting cycles.
2. Interrupt-driven: device raises the flag; CPU responds only when needed, freeing it for other work.

IX. LMC (Little Man Computer)

The Little Man Computer is a teaching simulator that models a von Neumann machine as a "little man" in a mailroom, making fetch–execute concrete for beginners.

A. Model and components

• 100 mailboxes: memory locations 00–99, each holding a 3-digit instruction or datum.
• Calculator: the accumulator for arithmetic.
• Program & instruction counter: tracks the next mailbox to read.
• In/Out baskets: input and output trays.

B. Instruction set and format

• Opcode + address: a leading digit is the operation, the last two digits the mailbox.
• Core mnemonics: LDA (5xx), STA (3xx), ADD (1xx), SUB (2xx), BRA (6xx), BRZ (7xx), BRP (8xx), INP (901), OUT (902), HLT (000).

C. Fetch–execute in the simulator

• Fetch: the little man reads the mailbox at the counter, then advances it.
• Execute: he decodes the digit and acts — loading, storing, adding, or branching.
• Pedagogic value: it mirrors the Basic Computer's cycle, registers and branching in decimal, so the abstract micro-operations above become directly observable.