Unit 2: Computer Organization - Practice Quiz

1 An instruction code is a group of bits that instruct the computer to perform a specific operation. Which part of the instruction code specifies the operation to be performed?

2 In a basic computer, an instruction code is generally divided into how many main parts?

3 The number of bits required for the operation code depends on the total number of what?

4 Which register holds the address of the next instruction to be executed?

5 In the basic computer, which register is used to hold an operand read from memory?

6 Which register in the basic computer holds the address of a memory location being accessed?

7 Which register holds the instruction that is currently being executed?

8 What is the main purpose of a common bus system in a computer?

9 In a common bus system, only one register can place its data on the bus at a time. This is controlled by what?

10 If a common bus has selection lines , how many registers or units can be selected?

11 The basic computer instructions are generally classified into how many categories?

12 Which type of instruction does not require a memory address to operate?

13 A memory-reference instruction uses one bit to indicate what?

14 The timing signals in a basic computer are generated by which component?

15 Which of the following is a type of control unit organization?

16 In timing and control, the master clock generator produces what?

17 The first phase of an instruction cycle is to do what?

18 After an instruction is fetched, what is the next step in the instruction cycle?

19 What is the main purpose of an interrupt in a computer system?

20 In the Little Man Computer (LMC) model, which component is used to perform arithmetic operations?

21 In a basic computer with a memory of 4096 words, each instruction uses a 12-bit address field and a 3-bit opcode with 1 addressing-mode bit. How many bits are unused for the memory-reference instruction format if the word size is 16 bits?

22 In the basic computer, the operation code (opcode) field is 3 bits wide. How many distinct memory-reference operations can be directly encoded before requiring register-reference or I/O instruction formats?

23 In the basic computer, the Program Counter (PC) and Address Register (AR) are both which width?

24 Which register in the basic computer holds the instruction currently being executed?

25 The INPR and OUTR registers in the basic computer are how many bits wide, matching a single character?

26 In the basic computer's common bus system with 8 registers plus memory selected by 3 bits (), which selection value places memory contents onto the bus?

27 How many selection lines are needed to choose one of the sources connected to a common bus that links 7 registers and memory (8 sources)?

28 In a common bus system built from multiplexers, what is the main advantage over a system with dedicated point-to-point connections between all registers?

29 The instruction (clear accumulator) in the basic computer is an example of which instruction type?

30 For a memory-reference instruction, if the addressing mode bit , what type of addressing is used?

31 In the basic computer, the instruction that stores the content of the accumulator into memory is:

32 In a hardwired control unit using a decoder driven by a sequence counter (SC), how many distinct timing signals through are available?

33 When the sequence counter (SC) is cleared with the control signal , which timing signal becomes active on the next clock?

34 What is the fundamental difference between a hardwired control unit and a microprogrammed control unit?

35 During the fetch phase, which micro-operation occurs at timing signal ?

36 At timing signal of the fetch cycle, which two micro-operations occur simultaneously?

37 After decoding at , if the instruction is a memory-reference type with , what happens at ?

38 In the basic computer, the interrupt enable flip-flop IEN is set and cleared by which pair of instructions?

39 When an interrupt occurs in the basic computer, the return address (contents of PC) is stored in memory location:

40 In the Little Man Computer (LMC), the instruction with opcode performs which operation?

41 In the basic computer, an instruction code has a 3-bit opcode field, allowing combinations. Yet the machine supports far more than 8 operations. How is this achieved without expanding the opcode field?

42 In Mano's basic computer, the memory has words of bits each. What are the required bit-widths of the Address Register () and the Data Register (), respectively?

43 The basic computer's common bus is controlled by three selection lines . If places contents on the bus and places memory contents on the bus, how many distinct sources can the bus select in total?

44 During the fetch phase, the microoperation occurs at and at . Why can't be moved to ?

45 An indirect memory-reference instruction adds one extra timing state () compared to a direct one. If the effective-address phase for a direct instruction completes decoding at , at which timing signal does execution of an indirect memory-reference instruction typically begin?

46 Consider the register-reference instruction (clear ) with hexadecimal code and (complement ) with code . What does the bit pattern reveal about how register-reference operations are encoded?

47 In the interrupt cycle, the return address is stored at memory location and control branches to location . Given the microoperations and followed by , what is the purpose of setting first?

48 The interrupt flip-flop is set only after both an I/O flag ( or ) and the interrupt-enable are , and additionally the current instruction cycle completes. Why is checked at the end of the execute phase rather than during fetch?

49 In the Little Man Computer, the instruction with opcode is LDA and opcode is STA. A program executes LDA 90 then ADD 91 then STA 92. If mailbox holds and mailbox holds , what value ends up in mailbox ?

50 The LMC accumulator can hold values from to . A program executes an ADD that would produce . What best describes the defined behavior in most LMC implementations?

51 The sequence counter is cleared to at the end of each instruction. If a memory-reference execute phase for a particular instruction ends at with the microoperation containing , what timing signal will be active at the start of the very next fetch?

52 A memory-reference instruction is encoded as in a 16-bit word. If an instruction has hexadecimal value , what are its addressing mode and opcode?

53 Suppose an operation requires transferring to over the common bus in a single clock. Which combination is required?

54 For the branch instruction BUN (branch unconditionally, direct mode), execution consists solely of . Considering fetch, decode, and effective address phases, how many timing states does a direct BUN consume in total from to completion?

55 A stored-program computer distinguishes data from instructions only by the phase in which a word is fetched. What consequence follows if the program counter accidentally points into a data region?

56 The 8-bit register (input) and (output) are narrower than the 16-bit . When executing INP, the transfer is . What happens to bits during this microoperation?

57 Under programmed I/O, the CPU polls the flag in a tight loop before reading each character. Compared with interrupt-driven I/O, what is the fundamental drawback of this approach?

58 A hardwired control unit derives each control signal as a Boolean function of the decoded opcode , timing signals , and status bits. Adding a new complex instruction to such a design is difficult primarily because:

59 An LMC program uses opcode for I/O: is INPUT and is OUTPUT. A loop reads a number, and branches back if the accumulator is not zero using (BRZ) and (BRA). Which construct correctly implements 'keep reading numbers until a zero is entered, then halt'?

60 Consider a memory-reference AND instruction with indirect addressing. Order the following phases correctly: (1) , (2) (indirect), (3) (fetch), (4) .