Unit 1: Introduction to Digital Systems and HDLs - Subjective Questions

Register Transfer Language (RTL) is a symbolic notation used to describe the internal micro-operations of digital systems by specifying the transfer of information among registers.

Basic Components:

• Registers: Denoted by capital letters (e.g., , , , ).
• Register bits: Individual bits shown as , , or ranges like .
• Common bus: Used to transfer data between registers.

Notation:

• The transfer statement means the content of register is copied into register .
• The arrow () denotes the transfer direction.
• Conditional transfer uses a control function: , meaning the transfer occurs only when control signal .
• Multiple transfers separated by commas occur simultaneously: .

Key Points:

• RTL provides a concise, precise way to describe hardware operations.
• It forms the foundation for designing the control logic of digital systems.
• The source register content remains unchanged after a transfer.

Bus Transfer refers to the transfer of information between registers through a shared set of common lines called a bus.

Concept:

• A bus is a group of wires that carries data from source register to destination register.
• Instead of dedicated wires between every pair of registers (which is expensive), a common bus shares lines among all registers.

Construction using Multiplexers:

• For registers each of bits, we need multiplexers, each of size .
• Selection lines determine which register's content is placed on the bus.
• For registers, selection lines are required.

Example: For 4 registers (A, B, C, D) of 4 bits each:

• Need 4 multiplexers of size .
• Need 2 selection lines ().

RTL notation: or simply .

Advantages:

• Reduces the number of wires.
• Cost-effective for systems with many registers.

Alternative: Three-state buffers (tri-state gates) can also be used to build bus systems more efficiently than multiplexers.

Memory Transfer involves transferring data between memory and processor registers.

Key Registers:

• MAR (Memory Address Register): Holds the address of the memory location to be accessed.
• MBR / MDR (Memory Buffer/Data Register): Holds the data being read from or written to memory.

Read Operation:

• Transfers information from a memory location into a register.
• RTL notation:
• Here denotes memory, is the address register holding the memory address, and is the destination data register.
• Steps: Place address in MAR → Activate read control → Data appears in MBR.

Write Operation:

• Transfers new information from a register into a memory location.
• RTL notation:
• Steps: Place address in MAR → Place data in MBR → Activate write control → Data stored in memory.

Points to Note:

• Memory is treated as an array addressed by the content of the address register.
• The read operation is non-destructive to the register content.
• These transfers are fundamental to instruction fetch and data access cycles.

A Shift Register is a sequential circuit consisting of a chain of flip-flops connected in cascade, capable of shifting binary data one bit at a time on each clock pulse.

Four Types of Shift Registers:

1. Serial In Serial Out (SISO):

   • Data enters serially (one bit per clock) and exits serially.
   • Used for time delay and serial data transfer.

2. Serial In Parallel Out (SIPO):

   • Data enters serially but all bits are available in parallel at the outputs.
   • Used for serial-to-parallel conversion.

3. Parallel In Serial Out (PISO):

   • Data loaded in parallel, output taken serially.
   • Used for parallel-to-serial conversion.

4. Parallel In Parallel Out (PIPO):

   • Data loaded and read out in parallel.
   • Used as temporary storage registers.

Bidirectional / Universal Shift Register:

• Can shift both left and right and perform parallel load.

Applications:

• Data storage and data movement.
• Serial-parallel conversions (communication systems).
• Arithmetic operations (multiplication/division by shifting).
• Sequence generators and counters.
• Time delay circuits.

Note: Each shift left multiplies a number by 2, and each shift right divides it by 2 (for unsigned numbers).

A Micro-operation is an elementary operation performed on the data stored in registers during one clock pulse period.

Classification of Micro-operations:

1. Register Transfer Micro-operations:

• Transfer binary information from one register to another without altering data.
• Example:

2. Arithmetic Micro-operations:

• Perform arithmetic on numeric data in registers.
• Examples:
  • Addition:
  • Subtraction:
  • Increment:
  • Decrement:

3. Logic Micro-operations:

• Perform bit-manipulation (logical) operations.
• Examples:
  • AND:
  • OR:
  • XOR:
  • Complement:

4. Shift Micro-operations:

• Shift the content of a register.
• Examples:
  • Logical shift left:
  • Logical shift right:
  • Circular and arithmetic shifts.

Summary: These four categories form the building blocks for all data processing operations executed by the CPU.

Arithmetic Micro-operations perform arithmetic operations on numeric data stored in registers.

Basic Arithmetic Micro-operations:

Binary Adder:

• Built by cascading full adders. For -bit addition, full adders are connected with carry propagation.

Binary Adder-Subtractor:

• Combines addition and subtraction into one circuit using an XOR gate at each input and a mode control signal .
• When : the circuit performs addition ().
• When : the circuit performs subtraction by adding the 2's complement of B, i.e., (the M signal complements B and provides the input carry).

Subtraction using 2's complement:

This unified circuit is efficient and forms the core of the ALU's arithmetic section.

Logic Micro-operations specify binary operations performed on the individual bits of the data stored in registers, treating each bit independently.

Common Logic Micro-operations:

• AND ():
• OR ():
• XOR ():
• Complement (NOT):

There are 16 possible logic operations for two variables.

Applications of Logic Micro-operations:

1. Selective Set:

• Sets to 1 the bits of register A where corresponding bits of B are 1.
• Uses OR operation:

2. Selective Complement:

• Complements bits of A where B has 1s.
• Uses XOR:

3. Selective Clear:

• Clears to 0 the bits in A where B has 1s.
• Operation:

4. Mask Operation:

• Clears selected bits (opposite of selective set); retains bits where mask B has 1s.
• Uses AND:

5. Insert Operation:

• Combines mask (AND) then OR to insert a new value into specific bit positions.

6. Clear Operation:

• Compares two words; produces all 0s when equal, using XOR.

These operations are essential for bit manipulation, flag handling, and data formatting.

Shift Micro-operations are used to transfer data laterally, shifting bits left or right. They are used for serial transfer, arithmetic, and data manipulation.

Three Types of Shifts:

1. Logical Shift:

• Transfers 0 into the vacated end position.
• Logical shift left (shl): All bits move left; 0 enters LSB.
• Logical shift right (shr): All bits move right; 0 enters MSB.
• Example: after shl = ; after shr = .

2. Circular Shift (Rotate):

• The bit shifted out at one end enters at the other end (no bit lost).
• Circular shift left (cil) and circular shift right (cir).
• Example: after cil = ; after cir = .

3. Arithmetic Shift:

• Shifts a signed number, preserving the sign bit.
• Arithmetic shift left (ashl): Multiplies signed number by 2; sign bit unchanged.
• Arithmetic shift right (ashr): Divides signed number by 2; sign bit is retained (sign extension).
• Example (8-bit, sign bit preserved): after ashr = .

Summary Table:

Overflow: In arithmetic shift left, overflow occurs if the sign bit changes.

In digital systems, signed numbers are commonly represented using 2's complement because it allows both addition and subtraction using the same adder circuit.

2's Complement Representation:

• MSB is the sign bit (0 = positive, 1 = negative).
• 2's complement of a number = 1's complement + 1.

Addition Rules:

• Add the two numbers including sign bits.
• Discard any carry out of the sign bit position.
• The result is in 2's complement form.

Example (Addition): in 4 bits

• (2's complement of 0100)
• Discard carry → ✓

Subtraction Rules:

• To compute , take the 2's complement of and add to .
  

Example (Subtraction):

• 2's complement of
• Discard carry → ✓

Overflow Detection:

• Overflow occurs when two numbers of the same sign produce a result of the opposite sign.
• Detected when carry into sign bit ≠ carry out of sign bit ().

Advantage: A single adder-subtractor circuit handles both operations, simplifying hardware.

Booth's Algorithm is an efficient method for multiplying signed binary numbers in 2's complement representation. It reduces the number of arithmetic operations by handling strings of 1s efficiently.

Registers Used:

• A (Accumulator, initialized to 0)
• Q (Multiplier)
• (extra 1-bit register, initialized to 0)
• M (Multiplicand)
• Count (number of bits, )

Algorithm Steps:

1. Initialize , , load M and Q, set count = n.
2. Examine the two bits :
   • If :
   • If :
   • If or : no arithmetic operation
3. Perform arithmetic shift right (ashr) on the combined register (sign bit preserved).
4. Decrement count.
5. Repeat steps 2–4 until count = 0.
6. The final product is in registers and .

Booth Encoding Rules:

Advantages:

• Handles both positive and negative numbers directly in 2's complement.
• Efficient for numbers with long strings of 1s or 0s.
• Reduces the number of add/subtract operations.

Disadvantage:

• Inefficient for isolated 1s (alternating bits), requiring frequent operations.

Given: Multiplicand and Multiplier (4-bit).

Representation:

• (2's complement)
• Initialize , , count = 4.

Step-by-Step Table:

Result: The product is in .

Verification:

• in 2's complement = .
• Check: ✓

The algorithm correctly produces , demonstrating Booth's ability to handle signed multiplication.

A Hardware Description Language (HDL) is a specialized computer language used to describe the structure, behavior, and timing of digital electronic circuits and systems. Unlike software languages, HDLs model concurrent hardware and physical timing.

Purpose of HDLs:

• Describe digital circuits at various abstraction levels (behavioral, RTL, gate).
• Enable simulation to verify functionality before fabrication.
• Enable synthesis to automatically generate actual hardware (gates/netlists).

History and Evolution:

• 1970s: Early HDLs emerged for documentation and simulation. Languages like ISP (Instruction Set Processor) and AHPL were developed academically.
• 1980s:
  • VHDL (VHSIC Hardware Description Language) developed by the U.S. Department of Defense (1983) under the VHSIC program. Standardized as IEEE 1076 in 1987.
  • Verilog developed by Gateway Design Automation (Phil Moorby, 1984) as a proprietary language, later acquired by Cadence.
• 1990s:
  • Verilog was opened to the public (Open Verilog International) and standardized as IEEE 1364 in 1995.
  • Logic synthesis tools matured, making HDLs central to design.
• 2000s onwards:
  • SystemVerilog (IEEE 1800, 2005) extended Verilog with verification and OOP features.
  • SystemC enabled higher-level system modeling.

Modern Trends:

• Higher levels of abstraction (High-Level Synthesis from C/C++).
• Verification-focused languages and methodologies (UVM).

Conclusion: HDLs evolved from simple documentation tools into powerful languages that drive the entire modern chip design flow.

The HDL-based design flow is the systematic process of designing a digital system from specification to a physical implementation using HDLs and EDA (Electronic Design Automation) tools.

Design Flow Stages:

Specification → Design (HDL Coding) → Simulation →
Synthesis → Verification → Physical Implementation

1. Design (HDL Coding):

• The digital system is described using an HDL (Verilog/VHDL) at the RTL (Register Transfer Level) or behavioral level.
• The designer specifies the functionality and structure.

2. Simulation (Functional Verification):

• The HDL code is simulated using a testbench to check functional correctness.
• Verifies whether the design behaves as intended before hardware realization.
• Types: pre-synthesis (behavioral) and post-synthesis (gate-level with timing).

3. Synthesis:

• The RTL description is converted (by a synthesis tool) into a gate-level netlist using a target technology library.
• Optimizes for area, speed, and power.
• Output: a netlist of logic gates and their interconnections.

4. Verification:

• Ensures the synthesized design meets specifications.
• Includes timing analysis (STA), formal verification, and gate-level simulation.
• Confirms the netlist is functionally equivalent to the RTL.

5. Physical Implementation:

• Placement, routing, and layout generation (for ASICs) or bitstream generation (for FPGAs).

Advantages of HDL-based Flow:

• Automation reduces design time and errors.
• Enables reuse and early bug detection.
• Technology-independent design at RTL level.

Conclusion: This structured flow allows complex chips with millions of gates to be designed efficiently and reliably.

While HDLs and software programming languages may look syntactically similar, they serve fundamentally different purposes. HDLs describe hardware, whereas software languages describe sequential instructions for a processor.

Comparison Table:

Key Conceptual Differences:

• Concurrency: In HDL, all always blocks and continuous assignments run in parallel, mirroring real hardware. In software, execution is line-by-line.
• Time: HDLs model propagation delays and clock edges; software has no such notion natively.
• Realization: HDL code becomes physical silicon; software code becomes instructions executed on existing hardware.

Conclusion: HDLs require a hardware mindset (thinking in terms of parallel logic and timing), which is the primary distinction from procedural software programming.

Verilog is a Hardware Description Language (HDL) used to model, design, simulate, and synthesize digital electronic systems. It was standardized as IEEE 1364.

Key Features:

• Supports multiple abstraction levels in a single language.
• C-like syntax, making it easy to learn.
• Supports both concurrent and sequential constructs.
• Widely used for ASIC and FPGA design.

Levels of Abstraction in Verilog:

1. Behavioral/Algorithmic Level: Describes what the circuit does using high-level constructs (always, if, case).
2. Dataflow (RTL) Level: Describes data flow using continuous assignments (assign).
3. Gate Level (Structural): Describes circuit using primitive gates (and, or, not).
4. Switch Level: Lowest level using transistors (rarely used).

Basic Structure of a Verilog Module:
verilog
module module_name (port_list);
// Port declarations
input a, b;
output y;

// Internal signal declarations
wire temp;

// Functionality (dataflow / behavioral / structural)
assign y = a & b;

endmodule

Example — 2-input AND gate:
verilog
module and_gate (input a, input b, output y);
assign y = a & b;
endmodule

Data Types:

• net (e.g., wire): represents physical connections.
• register (e.g., reg): stores values, used in procedural blocks.

Conclusion: Verilog's flexibility across abstraction levels and its concurrent modeling make it one of the most popular HDLs in the industry.

A 4-bit adder-subtractor performs both addition and subtraction using a single circuit controlled by a mode signal .

Circuit Construction:

• Uses 4 full adders connected in cascade.
• Each B input passes through an XOR gate with the mode control signal .
• is also connected to the carry-in () of the least significant full adder.

Working Principle:

Case 1: Addition ():

• XOR with 0 leaves B unchanged: .
• Carry-in .
• Circuit computes:

Case 2: Subtraction ():

• XOR with 1 complements B: .
• Carry-in .
• Circuit computes:
• (2's complement subtraction)

Mode Control Table:

RTL Description:

Overflow Detection:

• Overflow (carry into and out of MSB).

Advantage: A single circuit efficiently handles both operations, reducing hardware — the basis of the ALU's arithmetic unit.

Combinational vs Sequential Circuits:

Relation to RTL:

• Register Transfer Language (RTL) describes operations that involve registers, which are sequential (memory) elements.
• RTL statements like occur on clock edges, inherently defining sequential behavior.
• The control functions and timing signals in RTL are governed by sequential logic (state machines).

Relation to Shift Registers:

• Shift registers are prime examples of sequential circuits — built from cascaded flip-flops.
• On each clock pulse, data shifts, meaning the next state depends on the present state and input.
• Shift micro-operations in RTL (e.g., ) are physically implemented using shift registers.

Conclusion: RTL provides the notation, while sequential circuits (registers, shift registers) provide the physical hardware that stores and transfers information under clock control, forming the backbone of digital system design.

A Universal Shift Register can perform four operations: hold, shift left, shift right, and parallel load, selected by control lines .

Mode Selection Table:

Verilog Code:
verilog
module universal_shift_reg (
input clk,
input reset,
input [1:0] s, // mode select
input [3:0] p_in, // parallel input
input left_in, // serial input for left shift
input right_in, // serial input for right shift
output reg [3:0] q
);
always @(posedge clk or posedge reset) begin
if (reset)
q <= 4'b0000;
else begin
case (s)
2'b00: q <= q; // Hold
2'b01: q <= {right_in, q[3:1]}; // Shift Right
2'b10: q <= {q[2:0], left_in}; // Shift Left
2'b11: q <= p_in; // Parallel Load
endcase
end
end
endmodule

Functionality Explanation:

• Hold (00): Output retains its value.
• Shift Right (01): Bits move right; right_in enters MSB position.
• Shift Left (10): Bits move left; left_in enters LSB position.
• Parallel Load (11): All 4 bits loaded simultaneously from p_in.

Note: The always @(posedge clk) block models synchronous sequential behavior, and the concurrent nature of Verilog ensures the register updates on each clock edge.

A three-state buffer (tri-state gate) is a digital device with three output states: logic 0, logic 1, and a high-impedance (Z) state. The high-impedance state effectively disconnects the output from the bus.

Three-State Buffer Working:

• Has a data input, output, and a control (enable) input.
• When enable = 1: output follows input (0 or 1).
• When enable = 0: output is in high-impedance (Z) state (disconnected).

Common Bus using Three-State Buffers:

• Each register's output is connected to the bus through three-state buffers.
• Only one buffer is enabled at a time, placing that register's data on the bus.
• A decoder is used to ensure only one register drives the bus at any instant.

Construction for registers of bits:

• Requires groups of three-state buffers.
• A decoder with selection lines enables the appropriate group.

Comparison with Multiplexer-based Bus:

Advantage: Three-state buffer buses reduce circuit complexity and are widely used in microprocessor system buses.

Caution: If two buffers are enabled simultaneously, bus contention occurs, potentially damaging the circuit.

An arithmetic circuit can be designed to perform several arithmetic micro-operations by controlling the second input to a parallel adder.

Basic Idea:

• Use a 4-bit parallel adder.
• The first input is register A (unchanged).
• The second input Y is derived from register B through logic controlled by selection lines and the input carry .

General Equation:

where is a function of controlled by selection lines.

Deriving Operations by Controlling Y and :

Circuit Components:

• 4 full adders for the parallel addition.
• 4 multiplexers (one per bit) to select input as , , all-0s, or all-1s based on .

Explanation:

• Addition: , → .
• Subtraction: , → .
• Increment: , → .
• Decrement: (all 1s = -1), → .

Conclusion: By manipulating just the second input and carry, a single compact circuit performs seven distinct arithmetic operations, forming the arithmetic section of the ALU.