Unit 1: Introduction to Digital Systems and HDLs

CSE211 — Computer Organization And Design 7 min read

A digital system is a collection of registers and the logic that transfers and transforms binary data between them under the control of timing signals. This unit hangs on one governing idea: complex hardware is described as microoperations on registers, and modern practice captures those descriptions in a Hardware Description Language (HDL) rather than schematics.

Register: a group of flip-flops storing an n-bit word; the atomic unit of storage in the datapath.
Microoperation: an elementary operation on register data completed in one clock pulse (load, shift, add, clear).
Clock-driven timing: transfers occur on active clock edges gated by control signals.
Two-part machine: a datapath (registers, buses, ALU) plus a control unit that issues the enabling signals.
Description over drawing: HDLs let the same text be simulated, synthesised and verified.

II. Register Transfer Language

A symbolic notation for register-level operations.

A. Register Transfer Language

Register Transfer Language (RTL) names registers and the conditional transfers between them.

Register naming: capital letters, e.g. MAR, R1, PC; individual bits as R1[0].
Transfer statement: R2 ← R1 copies R1 into R2 while R1 is unchanged.
Conditional transfer: control condition precedes a colon.
- Form: P: R2 ← R1 means transfer occurs only when control signal P = 1.
Concurrency: operations separated by commas execute simultaneously — T: R1 ← 0, R2 ← R3.
Register width notation: PC(H) ← R1, PC(L) ← R2 addresses high and low bytes.

III. Bus and Memory Transfer

Shared paths for moving words efficiently.

A. Bus and Memory Transfer

A bus is a common set of lines that any selected register can drive, avoiding one wire per register pair.

Multiplexer bus: k registers of n bits share n multiplexers, each with k data inputs; select lines choose the source.
- Selection: to send R2 onto the bus and load R1: BUS ← R2, R1 ← BUS, abbreviated R1 ← R2.
Three-state buffer bus: each register output feeds a tri-state gate; enabling one gate drives the bus, others held in high-impedance Z.
Memory read: DR ← M[AR] — data register receives the word at the address in AR.
Memory write: M[AR] ← R1 — the word in R1 is stored at address AR.

IV. Shift Registers

Registers that move bits laterally per clock.

A. Shift Registers

A shift register is a cascade of flip-flops whose output feeds the next stage, shifting the word one position each pulse.

Serial input/output: one bit enters and one leaves per clock — used for serial data and delay lines.
Bidirectional register: control selects left or right shift; add a parallel-load path to build a universal shift register.
Serial transfer example: two 4-bit registers with Shr control move A into B in four clocks:
TEXT
```
  T1..T4:  A ← shr(A),  B ← shr(B),  B[3] ← Aout,  A[3] ← serial-in
```
Function table modes: 00 no change, 01 shift right, 10 shift left, 11 parallel load.

V. Microoperations

The three functional classes of register operation.

A. Arithmetic microoperations

These perform numeric operations on register contents.

Add / subtract: R3 ← R1 + R2, R3 ← R1 + R̄2 + 1 (2's-complement subtraction).
Increment / decrement: R1 ← R1 + 1, R1 ← R1 − 1, realised with counters.
Complement: R2 ← R̄2 (1's complement); adding 1 gives 2's complement.

B. Logic microoperations

These treat bits independently, applying Boolean functions bitwise.

AND (mask): R1 ← R1 ∧ R2 clears selected bits where R2 has 0s.
OR (set): R1 ← R1 ∨ R2 sets bits where R2 has 1s.
XOR (toggle): R1 ← R1 ⊕ R2 complements bits where R2 has 1s.
Selective operations: mask, insert and clear are built from AND/OR/XOR.

C. Shift microoperations

These reposition bits for serial transfer and arithmetic scaling.

Logical shift: R ← shl R / shr R — vacated end filled with 0.
Circular shift (rotate): end bit wraps around — cil, cir.
Arithmetic shift: ashl multiplies by 2, ashr divides by 2 while preserving the sign bit.

VI. Addition and Subtraction

The arithmetic core of the ALU.

A. Addition

Addition is done by chaining full adders, each summing two bits and a carry.

Full adder: S = x ⊕ y ⊕ c, c_out = xy + (x⊕y)c.
Ripple-carry adder: n full adders in series; carry propagates stage to stage.
Overflow (signed): detected when c_n ⊕ c_{n-1} = 1 — carry into and out of the sign bit differ.

B. Subtraction

Subtraction reuses the adder via complement arithmetic.

2's-complement rule: A − B = A + (B̄ + 1).
Add/subtract circuit: control bit M feeds XOR gates on B and the input carry; M=0 adds, M=1 subtracts.
Worked example: 5 − 3 in 4 bits — 0101 + (1100 + 1) = 0101 + 1101 = 1 0010; discard carry → 0010 = 2.

VII. Booth Multiplication

Signed multiplication by inspecting bit pairs.

A. Booth Multiplication

Booth's algorithm multiplies two signed 2's-complement numbers, reducing additions across strings of identical bits.

Registers: A (0), Q (multiplier), Q_{-1} (0), M (multiplicand), counter = n.
Recoding rule on (Q0, Q_{-1}):
- 10: A ← A − M (start of a 1-string).
- 01: A ← A + M (end of a 1-string).
- 00 / 11: no add — skip runs of like bits.
Then arithmetic shift right A, Q, Q_{-1} and decrement the counter.
Worked example: (−3) × (+2), M=1101, Q=0010, four steps of examine-then-ashr yield A,Q = 11111010 = −6.

VIII. Introduction to HDLs

Text-based description of hardware.

A. History

HDLs arose to manage rising chip complexity that schematics could no longer handle.

1980s origin: Verilog created at Gateway Design Automation (1984); VHDL developed under the US DoD VHSIC program.
Standardisation: VHDL → IEEE 1076 (1987); Verilog → IEEE 1364 (1995).

B. Evolution

HDLs grew from simulation aids into full synthesis and verification languages.

Feature growth: Verilog 2001 added generate blocks and signed arithmetic.
SystemVerilog (IEEE 1800, 2005): unified design and verification with assertions and OOP testbench constructs.
Higher abstraction: later flows add high-level synthesis from C/C++.

C. Typical HDL-based Design Flow (Design, Simulation, Synthesis, Verification)

The flow turns an HDL description into a working circuit through defined stages.

1. Design: capture behaviour/structure as RTL in Verilog or VHDL against a specification.
2. Simulation: run the model with testbench stimulus to check functional correctness before hardware.
3. Synthesis: a tool maps RTL to a gate-level netlist using a target technology library, optimising area, timing, power.
4. Verification: confirm the netlist matches intent via functional coverage, timing analysis and gate-level simulation.

D. Comparison with Software Programming Languages

HDLs and software languages share syntax style but model fundamentally different execution.

Software language: statements execute sequentially on one processor; describes an algorithm over time.
HDL: modules describe concurrent hardware — many blocks are active every clock edge in true parallelism.
- Time model: HDLs carry explicit timing, delays and clock edges; software has none intrinsically.
- Output: compiling software yields machine instructions; synthesising an HDL yields physical gates and wires.

IX. Verilog

The C-like HDL for design and verification.

A. Verilog

Verilog describes hardware as interconnected modules with ports, signals and concurrent behaviour.

Module structure: the design unit with a port list.

VERILOG

  module adder(input [3:0] a, b,
               input cin,
               output [3:0] sum,
               output cout);
    assign {cout, sum} = a + b + cin;
  endmodule

Data types: wire for continuous connections, reg for values held in procedural blocks.
Modelling styles:
- Dataflow: assign with continuous expressions.
- Behavioural: always blocks with if/case, e.g. always @(posedge clk).
- Structural: instantiate and wire sub-modules (gate primitives and, or).
Blocking vs non-blocking: = executes in order within a block; <= updates concurrently, used for sequential (clocked) logic.
Sensitivity list: always @(*) for combinational logic; edge lists for flip-flops.