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Unit 1: Introduction to Digital Systems and HDLs - Practice Quiz

CSE211 — Computer Organization And Design 60 Questions
0 Correct 0 Wrong 60 Left
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1 In Register Transfer Language (RTL), what does the statement mean?

Register Transfer Language Easy
A. Contents of are copied into
B. and are added together
C. and are swapped
D. Contents of are copied into

2 Which symbol is used to denote a register transfer operation in RTL?

Register Transfer Language Easy
A.
B.
C.
D.

3 In the RTL statement , what does represent?

Register Transfer Language Easy
A. The destination register
B. A control condition that must be true
C. A memory address
D. An arithmetic operation

4 What is the main purpose of a common bus in a digital system?

Bus and Memory Transfer Easy
A. To increase the clock frequency
B. To perform arithmetic operations
C. To store data permanently
D. To share a common path for data transfer among registers

5 In memory transfer, the statement refers to the memory word selected by which register?

Bus and Memory Transfer Easy
A. The Data Register (DR)
B. The Program Counter (PC)
C. The Accumulator (AC)
D. The Address Register (AR)

6 Which components are commonly used to construct a bus system?

Bus and Memory Transfer Easy
A. Flip-flops only
B. Shift registers
C. Adders
D. Multiplexers

7 What is the primary function of a shift register?

Shift Registers Easy
A. To store the memory address
B. To add two binary numbers
C. To shift stored bits left or right
D. To decode instructions

8 In a circular (ring) shift, the bit shifted out from one end is:

Shift Registers Easy
A. Fed back into the other end
B. Replaced with a
C. Discarded completely
D. Replaced with a

9 Which type of shift register accepts data one bit at a time?

Shift Registers Easy
A. Serial-in shift register
B. Parallel-in shift register
C. Random-access register
D. Content-addressable register

10 Which of the following is an example of a logic microoperation?

Micro operations (Arithmetic, logic, shift) Easy
A. AND operation on register contents
B. Adding two registers
C. Circular shift of a register
D. Incrementing a register

11 The four basic categories of microoperations are register transfer, arithmetic, logic, and:

Micro operations (Arithmetic, logic, shift) Easy
A. Decode
B. Fetch
C. Interrupt
D. Shift

12 Which microoperation is represented by ?

Micro operations (Arithmetic, logic, shift) Easy
A. Complement
B. Clear
C. Decrement
D. Increment

13 A full adder produces which two outputs?

Addition Easy
A. Product and Carry
B. Quotient and Remainder
C. Sum and Borrow
D. Sum and Carry

14 What is the result of the binary addition in a single-bit adder?

Addition Easy
A. Sum , Carry
B. Sum , Carry
C. Sum , Carry
D. Sum , Carry

15 Binary subtraction in computers is commonly performed using:

Subtraction Easy
A. Direct borrowing only
B. Logical AND operation
C. 2's complement addition
D. Repeated left shifts

16 To find the 2's complement of a binary number, you take its 1's complement and then:

Subtraction Easy
A. Complement it again
B. Shift it left
C. Subtract
D. Add

17 Booth's algorithm is used to perform which operation?

Booth Multiplication Easy
A. Addition of decimal numbers
B. Division of unsigned numbers
C. Logic comparison of registers
D. Multiplication of signed binary numbers

18 Booth's multiplication algorithm examines pairs of bits to decide the action. Which bits does it inspect at each step?

Booth Multiplication Easy
A. The current and previous bit of the multiplier
B. The sign bits of both operands
C. The two least significant bits of the multiplicand
D. The two most significant bits of the product

19 What does the abbreviation HDL stand for?

Introduction to HDLs: History, Evolution Easy
A. Hybrid Digital Language
B. Hardware Description Language
C. Hardware Design Logic
D. High-level Data Language

20 In an HDL design flow, which step converts the HDL description into an actual gate-level circuit?

Typical HDL-based Design Flow (Design, Simulation, Synthesis, Verification) Easy
A. Synthesis
B. Documentation
C. Simulation
D. Verification

21 Consider the RTL statement: . Assuming this is executed as a single register transfer controlled by condition , what is the effect?

Register Transfer Language Medium
A. The contents of and are swapped
B. Both and hold the old value of
C. Both and hold the old value of
D. The transfer is invalid and rejected

22 In the conditional RTL statement , what does the symbol represent?

Register Transfer Language Medium
A. A constant added to the register contents
B. The destination register for the data
C. A control function that enables the transfer when
D. A memory address pointer used for indexing

23 A common bus is built for 4 registers, each of 8 bits, using multiplexers. How many multiplexers and how many selection lines are required?

Bus and Memory Transfer Medium
A. 4 multiplexers and 2 selection lines
B. 2 multiplexers and 4 selection lines
C. 8 multiplexers and 2 selection lines
D. 8 multiplexers and 3 selection lines

24 The memory read micro-operation is written as . What is the role of in this operation?

Bus and Memory Transfer Medium
A. It supplies the address of the memory word to be read
B. It counts the number of read cycles performed
C. It holds the instruction to be executed next
D. It stores the data word read from memory

25 A 4-bit register holds the value . After one logical left shift with a 0 inserted, what does it contain?

Shift Registers Medium
A.
B.
C.
D.

26 An 8-bit register contains . After an arithmetic right shift by one position, the result is:

Shift Registers Medium
A.
B.
C.
D.

27 In a circular shift (rotate) left operation on the 4-bit value , what is the result?

Shift Registers Medium
A.
B.
C.
D.

28 Which micro-operation is represented by ?

Micro operations (Arithmetic, logic, shift) Medium
A. Arithmetic increment of
B. One's complement (bitwise NOT) of
C. Two's complement (negation) of
D. Logical AND of with itself

29 To selectively clear the bits in register wherever the corresponding bits in register are 1, which logic micro-operation is used?

Micro operations (Arithmetic, logic, shift) Medium
A.
B.
C.
D.

30 The XOR micro-operation is commonly used to perform which selective bit operation?

Micro operations (Arithmetic, logic, shift) Medium
A. Selective set of bits in where is 1
B. Masking of bits in where is 0
C. Selective clear of bits in where is 1
D. Selective complement (toggle) of bits in where is 1

31 Two 4-bit numbers and are added in a signed system. What is the result and does signed overflow occur?

Addition Medium
A. Result , overflow occurs
B. Result , no overflow
C. Result , no overflow
D. Result , overflow occurs

32 In an -bit adder, signed (two's complement) overflow is detected by:

Addition Medium
A. Comparing the carry into the sign bit with the carry out of the sign bit
B. Checking whether the final carry-out is 1
C. Checking whether the result equals zero
D. Comparing the MSBs of the two operands only

33 Using two's complement arithmetic, the subtraction on 4-bit numbers is performed as:

Subtraction Medium
A. , giving
B. , giving
C. , giving
D. , giving

34 In a parallel adder-subtractor circuit, subtraction is achieved by XORing with a mode line and setting the initial carry-in . What values of and enable subtraction?

Subtraction Medium
A. and
B. and
C. and
D. and

35 In Booth's algorithm, the pair of bits indicates which action before the arithmetic shift?

Booth Multiplication Medium
A. No arithmetic operation, only shift
B. Add the multiplicand ()
C. Subtract the multiplicand ()
D. Add the two's complement of the accumulator

36 The main advantage of Booth's multiplication algorithm over simple sequential add-and-shift multiplication is that it:

Booth Multiplication Medium
A. Works only for unsigned numbers but with higher speed
B. Always guarantees fewer than total additions regardless of input
C. Directly handles signed (two's complement) numbers and reduces operations for strings of consecutive 1s
D. Eliminates the need for any shift operations entirely

37 Verilog HDL was originally developed and later standardized by the IEEE. Under which IEEE standard was Verilog first standardized in 1995?

Introduction to HDLs: History, Evolution Medium
A. IEEE 802
B. IEEE 754
C. IEEE 1076
D. IEEE 1364

38 In a typical HDL-based design flow, which step converts the RTL description into a gate-level netlist mapped to a target technology?

Typical HDL-based Design Flow (Design, Simulation, Synthesis, Verification) Medium
A. Verification
B. Simulation
C. Synthesis
D. Specification

39 A key conceptual difference between an HDL like Verilog and a software language like C is that HDL constructs primarily:

Comparison with Software Programming Languages Medium
A. Describe concurrent hardware behavior that executes in parallel
B. Cannot represent time or delays in any form
C. Are always interpreted rather than compiled
D. Execute strictly one statement after another in sequence

40 In Verilog, which assignment type inside an always block models sequential (flip-flop) behavior by scheduling updates at the end of the time step?

Verilog Medium
A. Blocking assignment (=)
B. Continuous assignment (assign)
C. Procedural continuous assignment (force)
D. Non-blocking assignment (<=)

41 Consider the RTL statement: . If both transfers are triggered by the same control signal on the same clock edge, what is the net effect?

Register Transfer Language Hard
A. The contents of and are swapped
B. Both registers end up holding the original value of
C. Both registers end up holding the original value of
D. The operation is invalid and cannot be synthesized

42 A control function is written as . What is the minimum hardware condition required to clear register ?

Register Transfer Language Hard
A. Both AND must be true simultaneously
B. Either ( AND ) or ( AND ) must be true
C. Only AND must be true
D. All of , , , must be true

43 A system uses a common bus built from multiplexers to connect 4 registers, each bits wide. How many multiplexers and how many total selection lines are required?

Bus and Memory Transfer Hard
A. multiplexers and selection lines
B. multiplexers and selection lines
C. multiplexers and selection lines
D. multiplexers and selection lines

44 Given the memory transfer , which sequence of internal actions correctly represents this write operation?

Bus and Memory Transfer Hard
A. Place on address bus, on data bus, then assert Write
B. Place on address bus, on data bus, then assert Read
C. Place on data bus and on address bus simultaneously
D. Assert Read first, then place on the data bus

45 A 4-bit register holds . It is configured as a circular shift-right register. After 6 circular right shifts, what does the register contain?

Shift Registers Hard
A.
B.
C.
D.

46 A bidirectional shift register with parallel load requires selecting among 4 operations (no change, shift right, shift left, parallel load). What size multiplexer per flip-flop and how many mode-control lines are needed?

Shift Registers Hard
A. MUX with mode-control lines
B. MUX with mode-control line
C. MUX with mode-control lines
D. MUX with mode-control lines

47 A linear feedback shift register (LFSR) of length using an XOR feedback tap that produces a maximal-length sequence cycles through how many distinct states?

Shift Registers Hard
A. states
B. states
C. states
D. states

48 In an arithmetic circuit, the input to the adder is controlled so that becomes and the input carry . If , which micro-operation is realized?

Micro operations (Arithmetic, logic, shift) Hard
A. (increment)
B. (simple addition)
C. (reverse subtraction)
D. (subtraction via 2's complement)

49 A selective-complement micro-operation is defined as . If and , what is the result, and which bits of get toggled?

Micro operations (Arithmetic, logic, shift) Hard
A. Result ; no bits toggled
B. Result ; all bits toggled
C. Result ; bits where are toggled
D. Result ; bits where are toggled

50 For an 8-bit register holding interpreted as a signed 2's complement number, what value results from one arithmetic shift right, and is the sign preserved?

Micro operations (Arithmetic, logic, shift) Hard
A. ; sign bit becomes positive
B. ; sign bit is preserved (still negative)
C. ; a 1 is inserted at the LSB
D. ; sign bit is lost

51 In a 4-bit ripple-carry adder, if each full adder has a propagation delay of ns for sum and ns for carry, what is the worst-case delay for the most significant sum bit to become valid?

Addition Hard
A. ns
B. ns
C. ns
D. ns

52 Two signed 4-bit 2's complement numbers and are added. What is the result and does overflow occur?

Addition Hard
A. ; no overflow, result is valid
B. ; overflow occurs (result appears negative)
C. with carry out; no overflow
D. ; overflow occurs

53 Perform where and using 2's complement subtraction in 4 bits. What is the result and what does the carry-out indicate?

Subtraction Hard
A. ; end carry indicates overflow
B. ; end carry of 1 indicates a positive result
C. ; end carry indicates borrow
D. ; no end carry indicates the result is negative

54 In an unsigned subtraction using 2's complement, the presence of an end-carry (carry-out of 1) means what about the relationship between and ?

Subtraction Hard
A. Overflow has occurred and the result is invalid
B. , and the result is the correct positive difference
C. exactly
D. , and the result must be re-complemented

55 Using Booth's algorithm to multiply multiplier , how many arithmetic operations (additions or subtractions of the multiplicand) are performed?

Booth Multiplication Hard
A. operations (only shifts)
B. operations (one per bit)
C. operations (all subtractions)
D. operations (one subtract, one add)

56 Booth's algorithm inspects the bit pair at each step. Which pair value causes the partial product accumulator to have the multiplicand added to it?

Booth Multiplication Hard
A.
B.
C.
D.

57 A key advantage of Booth's algorithm over standard sequential multiplication is that it:

Booth Multiplication Hard
A. Handles signed 2's complement operands directly and skips runs of identical bits
B. Eliminates the need for any shift operations
C. Always requires exactly additions for -bit operands
D. Only works correctly for unsigned positive numbers

58 In a typical HDL-based design flow, which stage transforms behavioral/RTL descriptions into an optimized gate-level netlist mapped to a target technology library?

Introduction to HDLs: History, Evolution, Typical HDL-based Design Flow (Design, Simulation, Synthesis, Verification) Hard
A. Timing back-annotation
B. Synthesis
C. Behavioral verification
D. Simulation

59 During functional simulation before synthesis, a design behaves correctly, but after synthesis the gate-level simulation shows glitches and timing failures. The most likely cause is:

Introduction to HDLs: History, Evolution, Typical HDL-based Design Flow (Design, Simulation, Synthesis, Verification) Hard
A. Use of non-synthesizable constructs or missing timing constraints not captured by pre-synthesis simulation
B. The testbench was written in a software language rather than an HDL
C. Functional simulation is always incorrect and should be skipped
D. The RTL code contained syntax errors ignored by the simulator

60 Consider the Verilog fragment inside an always block: a = b; c = a; versus a <= b; c <= a;. Assuming a, b, c are registers and this is the only block driving them, what is the key difference in outcome?

Comparison with Software Programming Languages Hard
A. Both produce identical results since Verilog ignores assignment type
B. Non-blocking assignments execute faster but give the same values as blocking
C. Blocking assignments cause to get the old value of
D. Blocking assigns update sequentially so gets new ; non-blocking schedule updates so gets old
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Unit 2