1What is the fundamental difference between a combinational circuit and a sequential circuit?
A.Combinational circuits have memory, while sequential circuits do not.
B.Sequential circuits depend only on present inputs, while combinational circuits depend on past outputs.
C.Sequential circuits contain memory elements and feedback paths, whereas combinational circuits do not.
D.Combinational circuits are slower than sequential circuits.
Correct Answer: Sequential circuits contain memory elements and feedback paths, whereas combinational circuits do not.
Explanation:Sequential circuits use memory elements (like flip-flops) to store past states, meaning their output depends on both present inputs and past outputs. Combinational circuits depend only on present inputs.
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2Which of the following serves as the basic building block of a sequential circuit?
A.Multiplexer
B.Decoder
C.Flip-Flop
D.Adder
Correct Answer: Flip-Flop
Explanation:A flip-flop (or latch) is a bistable multivibrator that serves as the basic memory element in sequential logic circuits.
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3What is the primary difference between a Latch and a Flip-Flop?
A.Latches are edge-triggered; Flip-Flops are level-triggered.
B.Latches are level-triggered; Flip-Flops are edge-triggered.
C.Latches cannot store data; Flip-Flops can.
D.Latches are synchronous; Flip-Flops are asynchronous.
Correct Answer: Latches are level-triggered; Flip-Flops are edge-triggered.
Explanation:A latch responds to the input levels as long as the enable signal is active (level-triggered). A flip-flop responds to inputs only at specific transitions of the clock signal (edge-triggered).
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4In a basic NOR-gate based SR latch, what happens when inputs and ?
A.The output toggles.
B.The output remains unchanged.
C.The output goes to a valid Set state.
D.The output becomes indeterminate (Invalid).
Correct Answer: The output becomes indeterminate (Invalid).
Explanation:In a NOR-based SR latch, if both and are High ($1$), both NOR outputs try to go Low ($0$), violating the complementary nature of and . This is a forbidden or invalid state.
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5For a NAND-gate based SR latch, which input condition constitutes the invalid state?
A.
B.
C.
D.
Correct Answer:
Explanation:NAND latches are active-low. When both inputs are $0$, both outputs are forced to logic $1$, which is invalid as and must be complementary.
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6What is the characteristic equation of an SR Flip-Flop?
A.
B.
C.
D.
Correct Answer:
Explanation:The next state becomes 1 if Set is 1, or if it was already 1 and Reset is not active. The equation is (given ).
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7In a clocked SR Flip-Flop, if , , and the clock pulse is applied, what is the next state ?
A.0
B.1
C. (No Change)
D. (Toggle)
Correct Answer: (No Change)
Explanation:When both inputs S and R are 0, the flip-flop maintains its previous state (Hold state).
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8What is the main disadvantage of the basic SR Flip-Flop?
A.It has no clock input.
B.It cannot store 0.
C.It has an invalid state when and .
D.It requires too many gates.
Correct Answer: It has an invalid state when and .
Explanation:The primary limitation of an SR flip-flop is the indeterminate state when both inputs are asserted simultaneously.
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9Which flip-flop is known as a 'Transparent Latch'?
A.SR Latch
B.JK Flip-Flop
C.D Latch
D.Master-Slave Flip-Flop
Correct Answer: D Latch
Explanation:A D (Data) Latch transmits the input D to the output Q immediately when the Enable signal is active, making it 'transparent'.
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10How is a D Flip-Flop constructed using an SR Flip-Flop?
A.Connect to and to .
B.Connect to and to (via an inverter).
C.Connect to and to .
D.Connect both and to ground.
Correct Answer: Connect to and to (via an inverter).
Explanation:To prevent the invalid state and ensure , an inverter is placed between the inputs. receives and receives .
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11What is the characteristic equation of a D Flip-Flop?
A.
B.
C.
D.
Correct Answer:
Explanation:In a D flip-flop, the next state simply follows the input D at the active clock edge. Thus, .
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12Which Flip-Flop is designed specifically to eliminate the invalid state of the SR Flip-Flop while allowing two data inputs?
A.D Flip-Flop
B.T Flip-Flop
C.JK Flip-Flop
D.Buffer Latch
Correct Answer: JK Flip-Flop
Explanation:The JK Flip-Flop modifies the SR architecture to allow the state, turning it into a 'Toggle' function instead of an invalid state.
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13In a JK Flip-Flop, what is the output status when and ?
A.No Change
B.Set to 1
C.Reset to 0
D.Toggle
Correct Answer: Toggle
Explanation:When both inputs are high (), the JK flip-flop inverts its current state (Toggles) upon the clock trigger.
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14What is the characteristic equation of a JK Flip-Flop?
A.
B.
C.
D.
Correct Answer:
Explanation:The next state logic for a JK flip-flop is derived as .
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15The 'Race-around condition' occurs in which type of flip-flop?
A.D Flip-Flop
B.Level-triggered JK Flip-Flop
C.Edge-triggered SR Flip-Flop
D.T Flip-Flop with
Correct Answer: Level-triggered JK Flip-Flop
Explanation:Race-around occurs in a level-triggered JK flip-flop when and the clock pulse width is longer than the propagation delay of the flip-flop, causing the output to oscillate multiple times.
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16Which of the following is a method to avoid the race-around condition?
A.Increasing the clock period.
B.Using a Master-Slave configuration.
C.Using a level-triggered circuit.
D.Connecting and to ground.
Correct Answer: Using a Master-Slave configuration.
Explanation:A Master-Slave flip-flop isolates the input from the output using two stages clocked by complementary signals, effectively preventing the multiple toggling (race-around) within one clock pulse.
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17In a Master-Slave JK flip-flop, when is the 'Master' active?
A.When the clock is High (level 1).
B.When the clock is Low (level 0).
C.During the negative edge.
D.Always.
Correct Answer: When the clock is High (level 1).
Explanation:Typically, the Master latch is enabled when (taking in data), and the Slave is enabled when (passing data to output). Note: This assumes positive logic gating structure.
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18How is a T (Toggle) Flip-Flop constructed from a JK Flip-Flop?
A.By connecting and .
B.By connecting and together to input .
C.By connecting to and to .
D.By connecting output back to inputs.
Correct Answer: By connecting and together to input .
Explanation:A T flip-flop is created by tying the J and K inputs together. When , (No Change). When , (Toggle).
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19What is the characteristic equation of a T Flip-Flop?
A.
B.
C.
D.
Correct Answer:
Explanation:If , . If , . This behavior corresponds to the Exclusive-OR operation: .
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20If a T Flip-Flop is toggled at every clock cycle, what is the relationship between the input clock frequency () and the output frequency ()?
A.
B.
C.
D.
Correct Answer:
Explanation:A T flip-flop with T=1 toggles on every active clock edge. It takes two clock cycles to complete one full cycle of the output (0 to 1 to 0). Thus, it divides the frequency by 2.
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21What are the excitation table values of and for a transition from state to ?
A.
B.
C.
D.
Correct Answer:
Explanation:To go from 0 to 1, we can either Set () or Toggle (). In both cases, must be 1, while can be 0 or 1 (Don't Care, X).
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22To convert an SR flip-flop into a JK flip-flop, what logic is required at the S input?
A.
B.
C.
D.
Correct Answer:
Explanation:To mimic JK behavior using SR: and . This feedback enables the toggling behavior.
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23What is the Setup Time () in the context of flip-flops?
A.The time the output takes to change after the clock edge.
B.The minimum time data must be stable after the clock edge.
C.The minimum time data must be stable before the active clock edge.
D.The time required to reset the flip-flop.
Correct Answer: The minimum time data must be stable before the active clock edge.
Explanation:Setup time is the specific duration the input data must remain stable before the triggering edge of the clock pulse to be reliably captured.
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24What is Hold Time ()?
A.The minimum time data must be stable after the active clock edge.
B.The time the clock pulse must stay high.
C.The propagation delay of the gate.
D.The time before the clock edge where data must be stable.
Correct Answer: The minimum time data must be stable after the active clock edge.
Explanation:Hold time is the interval after the clock transition during which the data input must be maintained constant.
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25Which inputs are known as 'asynchronous' or 'direct' inputs on a standard Flip-Flop?
A.J and K
B.D and Clock
C.Preset (PR) and Clear (CLR)
D.Master and Slave
Correct Answer: Preset (PR) and Clear (CLR)
Explanation:Preset and Clear inputs affect the state of the flip-flop immediately, independent of the clock signal, hence they are asynchronous.
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26To convert a JK Flip-Flop to a D Flip-Flop, the required input connections are:
A.
B.
C.
D.
Correct Answer:
Explanation:A D flip-flop sets () when and resets () when . By making and , the JK flip-flop behaves exactly this way.
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27In the excitation table of a D Flip-Flop, if the transition is , what is the required input ?
A.0
B.1
C.X (Don't Care)
D.Toggle
Correct Answer: 1
Explanation:Since , if the next state is 1, the input D must be 1.
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28In the excitation table of an SR Flip-Flop, for the transition , what are and ?
A.
B.
C.
D.
Correct Answer:
Explanation:To go from 1 to 0, the flip-flop must be Reset. The input condition for Reset is .
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29Which of the following is true for a positive edge-triggered flip-flop?
A.It responds to inputs when the clock is High.
B.It responds to inputs when the clock is Low.
C.It responds to inputs only during the Low-to-High transition of the clock.
D.It responds to inputs only during the High-to-Low transition of the clock.
Correct Answer: It responds to inputs only during the Low-to-High transition of the clock.
Explanation:Positive edge-triggering means the device samples inputs and updates outputs only at the rising edge (0 to 1 transition) of the clock.
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30When converting a D Flip-Flop to a T Flip-Flop, what is the expression for the D input?
A.
B.
C.
D.
Correct Answer:
Explanation:We want . Since for a D-FF, , we simply set .
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31What is the value of the 'X' (Don't Care) in the SR excitation table for the transition ?
A.S must be 0, R is X
B.S is X, R must be 0
C.S is X, R is X
D.S must be 1, R is X
Correct Answer: S must be 0, R is X
Explanation:To keep the state at 0, we can use No Change () or Reset (). In both cases , while can be 0 or 1 ().
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32Which type of triggering is most sensitive to noise on the clock line?
A.Positive Edge Triggering
B.Negative Edge Triggering
C.Level Triggering
D.Master-Slave Triggering
Correct Answer: Level Triggering
Explanation:Level triggering is transparent while the clock is active. Any noise glitch during the active level can change the output. Edge triggering only looks at the instant of transition.
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33In a Master-Slave flip-flop, the slave is essentially a:
A.Combinational Circuit
B.Negative edge-triggered latch
C.Follower that copies the master when the clock is inactive for the master
D.Pulse generator
Correct Answer: Follower that copies the master when the clock is inactive for the master
Explanation:The slave receives the output of the master. When the master is locked (clock transition), the slave opens to update the final output.
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34What is the propagation delay () in a flip-flop?
A.Time between input change and clock signal.
B.Time between clock edge and output change.
C.Time clock must remain high.
D.Time between J and K changes.
Correct Answer: Time between clock edge and output change.
Explanation:Propagation delay is the time interval between the triggering edge of the clock and the stabilization of the output to the new state.
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35Which statement regarding the T Flip-Flop is FALSE?
A.It can be built using a D Flip-Flop.
B.It has an invalid state.
C.It acts as a frequency divider.
D.It toggles when input T=1.
Correct Answer: It has an invalid state.
Explanation:A T flip-flop does not have an invalid state. is Hold, is Toggle. The SR latch is the one with the invalid state.
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36Which logic gate is required to convert a T Flip-Flop into a D Flip-Flop?
A.AND gate
B.OR gate
C.XOR gate
D.NAND gate
Correct Answer: XOR gate
Explanation:To convert T to D, we need the next state to be D. . We need to hold? No, we are converting into D from T (using a T flip flop to make a D). We need . The T FF equation is . We need . Solving for T: . Thus, an XOR gate is needed at the input.
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37When designing a counter, which flip-flop is generally preferred due to its toggle capability?
A.SR Flip-Flop
B.D Flip-Flop
C.T Flip-Flop (or JK in toggle mode)
D.Latch
Correct Answer: T Flip-Flop (or JK in toggle mode)
Explanation:Counters essentially toggle states based on sequences. T flip-flops (or JK connected as T) are naturally suited for this because of their simple toggling excitation.
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38What does the triangle symbol at the clock input of a flip-flop block diagram indicate?
A.Level Triggering
B.Edge Triggering
C.Asynchronous Input
D.Inverted Input
Correct Answer: Edge Triggering
Explanation:A triangle (dynamic indicator) at the control input signifies that the device is edge-triggered. Without a bubble, it is positive edge-triggered.
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39If a bubble (circle) is present along with the triangle at the clock input, it indicates:
A.Positive Edge Triggering
B.Negative Edge Triggering
C.Active High Level Triggering
D.Active Low Level Triggering
Correct Answer: Negative Edge Triggering
Explanation:The bubble indicates inversion. Combined with the triangle (edge), it denotes Negative Edge Triggering (High-to-Low).
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40In the conversion of a Flip-Flop, what is the first step?
A.Draw the logic diagram.
B.Write the characteristic equation of the destination flip-flop.
C.Create an excitation table combining the available FF inputs and the desired next state.
D.Minimize using K-Map.
Correct Answer: Create an excitation table combining the available FF inputs and the desired next state.
Explanation:The standard procedure involves drawing a conversion table that lists Present State, Inputs, Next State, and the required Excitation inputs for the available flip-flop.
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41What happens to the output of a JK flip-flop if ?
A.Sets to 1
B.Resets to 0
C.Toggles
D.Holds state
Correct Answer: Resets to 0
Explanation:In a JK flip-flop, stands for Kill/Reset. If and , the output becomes 0.
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42Why is the D flip-flop often called a 'Delay' flip-flop?
A.It is slower than other flip-flops.
B.The data at input D appears at output Q one clock pulse later.
C.It has a built-in delay element.
D.It delays the clock signal.
Correct Answer: The data at input D appears at output Q one clock pulse later.
Explanation:It captures the data at the clock edge and holds it for the duration of the cycle, effectively delaying the data transmission by one clock period.
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43For a logic circuit to be a sequential circuit, it must contain:
A.Logic gates only
B.Feedback loop
C.Clock signal
D.Both logic gates and a feedback loop (memory)
Correct Answer: Both logic gates and a feedback loop (memory)
Explanation:Sequential circuits require combinational logic (gates) to determine state changes and a feedback mechanism/memory element to store the current state.
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44The 'Enable' input in a Gated SR Latch behaves like:
A.A Clear input
B.A Clock (in level-triggered mode)
C.A Data input
D.A Preset input
Correct Answer: A Clock (in level-triggered mode)
Explanation:The Enable input gates the S and R signals. When Enable is high, the latch works; when low, the latch holds. This is effectively a level-sensitive clock.
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45Given a JK Flip-Flop, if we want to implement the function , what should be the value of ?
A.0
B.1
C.J
D.
Correct Answer: 1
Explanation:The JK equation is . To get only , the second term must be 0. This requires , so .
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46In a NAND-gate latch, the 'Hold' state is achieved when inputs are:
A.
B.
C.
D.
Correct Answer:
Explanation:NAND latches are active low. Logic 1 on inputs is the inactive state. Thus, maintains the previous state.
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47Which flip-flop is the most versatile and can be easily converted into others?
A.SR Flip-Flop
B.JK Flip-Flop
C.D Flip-Flop
D.T Flip-Flop
Correct Answer: JK Flip-Flop
Explanation:The JK flip-flop includes the Set, Reset, Hold, and Toggle functions, making it a superset of behavior for SR, D, and T flip-flops.
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48In a Master-Slave flip-flop circuit diagram, the Slave is usually clocked by:
A.The same clock as the Master.
B.An inverted version of the Master's clock.
C.The output of the Master.
D.A separate external clock.
Correct Answer: An inverted version of the Master's clock.
Explanation:To ensure they don't function simultaneously (which would cause race-around), the Slave receives the inverted clock of the Master.
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49The characteristic equation represents which state?
A.Set
B.Reset
C.Toggle
D.Hold/Memory
Correct Answer: Hold/Memory
Explanation:When the next state equals the current state, the circuit is 'Holding' or 'Remembering' the data.
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50What is the primary motivation for converting one type of flip-flop to another?
A.To reduce power consumption.
B.To utilize available hardware (e.g., using a JK chip to function as a D FF).
C.To increase switching speed.
D.To eliminate the need for a clock.
Correct Answer: To utilize available hardware (e.g., using a JK chip to function as a D FF).
Explanation:Flip-flop conversion is a design technique used when a specific type of flip-flop is needed for a design, but a different type is available in the hardware inventory.