Unit 5 - Practice Quiz

In an SR Latch, 'S' stands for Set, which sets the output Q to 1, and 'R' stands for Reset, which resets the output Q to 0.

A latch is a basic memory element that can store a single bit (1 or 0) of information. It holds this value until it is changed by the inputs.

The condition S=1, R=1 in a NOR-based SR latch forces both outputs (Q and Q') to 0, which violates the fundamental rule that Q and Q' must be complementary. This leads to an unpredictable state when the inputs return to 0.

A D Latch is called a transparent latch because when its enable input is active, the output (Q) follows the input (D) as if it were a simple wire, making the latch 'transparent'.

The main difference is that a flip-flop is a clocked, edge-triggered device, meaning its output changes only at a specific point on the clock signal (rising or falling edge). A latch is level-sensitive.

The JK flip-flop is an improvement over the SR flip-flop because it defines the input condition J=1, K=1 as the 'toggle' state, thus eliminating the ambiguous or invalid state.

When both inputs J and K are high (1), the output of the JK flip-flop toggles, meaning it flips to the opposite of its current state on the next active clock edge.

The 'T' in T flip-flop stands for Toggle. Its primary function is to change its output state (toggle) when the T input is high and a clock pulse occurs.

When T=0, the T flip-flop is in the 'no change' or 'hold' mode. The output Q remains the same as it was before the clock pulse.

A D (Data) flip-flop is designed to capture the value on its D input at the clock edge and hold that value at its output Q until the next clock edge. This makes it ideal for data storage and creating delays.

The master-slave configuration isolates the input from the output, preventing a situation where the output changes multiple times within a single clock pulse (race-around condition), which can occur in level-triggered JK flip-flops.

The master-slave architecture consists of two cascaded stages: the 'master' latch/flip-flop and the 'slave' latch/flip-flop, with opposite clock polarities to ensure proper operation.

The master accepts input when the clock is at one level (e.g., high), and the slave updates its output to match the master's output when the clock transitions to the other level (e.g., low). This makes it an edge-triggered device.

The master section is typically a level-triggered latch. In a positive level-triggered design, the master is active and accepts new input data when the clock level is high.

When J and K are tied together, the JK flip-flop has two states: J=K=0 (Hold) and J=K=1 (Toggle). This exactly mimics the behavior of a T flip-flop, where T=0 is hold and T=1 is toggle.

To make an SR flip-flop behave like a D flip-flop, we must ensure S and R are never 1 at the same time. By setting S = D and R = D', if D=1, S=1 and R=0 (Set). If D=0, S=0 and R=1 (Reset). This matches the behavior of a D flip-flop.

Sequential circuits have memory elements (like latches and flip-flops) that store the circuit's state. Therefore, the next output is a function of not only the current inputs but also the previously stored state (past outputs).

The characteristic equation simply means that the next state of the flip-flop's output (Q) will be equal to the value of the input (D) after the active clock edge.

The toggle mode of a JK flip-flop is activated when both J and K inputs are held high (1). This configuration is essentially how a T flip-flop is created with T held permanently high.

The 'Enable' input acts like a switch. The latch only responds to the S and R inputs when the Enable signal is active (e.g., high). When it is inactive, the latch holds its current state regardless of S and R.

For a NAND latch, S=0 and R=0 is the forbidden or invalid state. In this state, both NAND gates will output 1, because any input being 0 to a NAND gate results in a 1 output. This violates the fundamental property of a latch where Q and must be complements.

The term 'transparent' means that as long as the enable input is active (HIGH), the output Q follows the input D. Since the last value of D before the enable signal went LOW was 0, the output Q will be 0. The latch will then hold this 0 value after E goes LOW.

In an SR flip-flop, the input condition S=1 and R=1 is forbidden because it leads to an unpredictable or invalid output state where Q and might not be complementary. The JK flip-flop resolves this by defining the J=1, K=1 condition as the 'toggle' state.

A D flip-flop passes the value of the D input to the Q output on the triggering clock edge. If D is held constant at HIGH (1), then on every positive clock edge, Q will be set to 1. Since Q never changes after the first clock edge, it remains at a constant HIGH level, which corresponds to a frequency of 0 Hz.

A single T flip-flop, with its T input held HIGH, divides the clock frequency by 2. To divide by a factor of , N flip-flops are needed. To divide by 8, which is , we need a minimum of 3 T flip-flops connected in cascade.

The condition J=1, K=1 puts the JK flip-flop in toggle mode. The output Q will invert its state on each active clock edge. Starting with Q=0: After 1st pulse, Q becomes 1. After 2nd pulse, Q becomes 0. After 3rd pulse, Q becomes 1. After 4th pulse, Q becomes 0. The sequence is 1, 0, 1, 0.

The race-around condition occurs in level-triggered JK flip-flops when J=1, K=1, and the clock pulse width is longer than the propagation delay. The output may toggle multiple times during a single clock pulse. The Master-Slave configuration ensures that the output changes only once per clock cycle by isolating the input (master) from the output (slave).

The characteristic equation for a T flip-flop is . The characteristic equation for a D flip-flop is . To make the D flip-flop behave like a T flip-flop, we must set its D input such that of the T flip-flop. Therefore, we must connect the input D to the output of an XOR gate with inputs T and the flip-flop's current state Q, i.e., .

In a negative edge-triggered Master-Slave flip-flop, the master latch is active and samples the J and K inputs when the clock is HIGH. The slave latch is isolated during this time. When the clock transitions from HIGH to LOW (the negative edge), the master is disabled and its state is transferred to the slave latch, which then updates the final Q and outputs.

The race-around condition is specific to level-triggered JK flip-flops. When J=K=1 (toggle mode) and the clock is active (e.g., HIGH), the output Q toggles. If the clock remains active for longer than the flip-flop's propagation delay, the newly changed output is fed back to the input, causing another toggle. This oscillation continues until the clock becomes inactive, leading to an unpredictable final state.

We want the next state to be equal to D. The JK flip-flop's characteristic equation is . If we substitute J=D and K=, we get . Thus, the flip-flop's next state equals the D input.

A T flip-flop with T=1 toggles its output on every active clock edge. If the input clock is a symmetrical square wave, the flip-flop will change state on every negative edge. This results in an output square wave with exactly half the frequency and a 50% duty cycle, regardless of the input's duty cycle.

The fundamental distinction lies in their triggering mechanism. A latch is sensitive to the level of its control signal (e.g., enable). As long as the enable is active, the latch output can change with the inputs. A flip-flop is sensitive to the transition, or edge, of its control signal (the clock). It changes its output only at the moment the clock signal changes (e.g., from LOW to HIGH).

We need to derive the logic from the excitation tables. For a T flip-flop, if T=0, it holds state (S=0, R=0). If T=1, it toggles. If Q=0 and toggle is needed, Q must become 1 (Set, S=1, R=0). If Q=1 and toggle is needed, Q must become 0 (Reset, S=0, R=1). This behavior is achieved with S = T and R = TQ.

The master part of the flip-flop is level-sensitive. While the clock is HIGH (in a negative-edge triggered setup), the master is active and continuously samples the J and K inputs. It will hold the state corresponding to the values of J and K that were present just before the clock's falling edge. This final state of the master is then transferred to the slave on the falling edge.

Tying J and K inputs to HIGH configures each flip-flop to be in toggle mode. In a synchronous counter, all flip-flops are triggered by the same clock signal. The combinational logic between them determines which flip-flops toggle on a given clock pulse. The question implies a counter structure, and with J=K=1, it will indeed count synchronously. A ripple counter would have the output of one flip-flop clocking the next.

The goal is to make the T flip-flop's next state () match the JK flip-flop's next state (). We need to find the T input that causes a toggle when the JK would toggle. A toggle occurs when . This happens for JK when (J=1, Q=0) or (K=1, Q=1). Therefore, the T input should be HIGH for these conditions. This gives the expression T = J + KQ.

A gated D latch is transparent; its output changes whenever the input changes as long as the gate is enabled. This can cause timing problems in synchronous systems. An edge-triggered D flip-flop only samples the input and changes its output at the precise moment of a clock edge, ensuring that all state changes in a system happen simultaneously and predictably.

Because the master latch is level-sensitive, any momentary pulse to '1' on the S or J input while the clock is active can set the master latch. Even if the input goes back to 0, the master remains set. This 'caught' 1 is then transferred to the slave on the clock edge, which can be an unintended behavior. This is a disadvantage compared to pure edge-triggered flip-flops.

Let's analyze the two possible states. If the current state Q=0, then =1. The inputs to the flip-flop are J=0 and K=1. This is the reset condition, so the next state will be Q=0. If the current state Q=1, then =0. The inputs are J=1 and K=0. This is the set condition, so the next state will be Q=1. In both cases, the output does not change (), so the flip-flop holds its state.

The pulse duration is shorter than the propagation delay . This means the output of the NOR gates will not have enough time to change and propagate through the feedback loop before the inputs S and R return to 0. The latch effectively ignores these short pulses and remains in its previous state. The condition is not held long enough to force the outputs low.

The first JK flip-flop acts as a toggle flip-flop (T flip-flop with T=1), functioning as a frequency divider. A key property of this operation is that its output waveform () will have a perfect 50% duty cycle, regardless of the duty cycle of the input clock. This is because it changes state only on one type of clock edge (e.g., rising edge). The second flip-flop is clocked by this 50% duty cycle signal, and since it also divides the frequency by two, its output will also have a 50% duty cycle.

The characteristic equation for a D flip-flop is . The characteristic equation for a JK flip-flop is . To make the D flip-flop behave like a JK flip-flop, we must set its input D equal to the desired next state of the JK flip-flop. Therefore, we set of the JK flip-flop. This gives the required excitation logic expression .

This demonstrates the '1s catching' property of a master-slave flip-flop. While the clock is HIGH, the master latch is transparent. Initially, with J=K=1, the master's state is set to toggle (it will go to 1). The glitch on J has no effect as J is already 1. When the clock goes LOW, the slave latch copies the master's state (which is 1), so Q becomes 1. The key is that the master captures the J=1, K=1 condition while the clock is high, and this state is transferred to the slave on the falling edge.

The T input is given by . The next state of the T flip-flop is . Let's trace the states:

• Initial State: .
• After 1st clock pulse (X=1): Current Q is 0. . Since T=0, the flip-flop holds its state. .
• After 2nd clock pulse (X=0): Current Q is 0. . Since T=1, the flip-flop toggles. .
• After 3rd clock pulse (X=1): Current Q is 1. . Since T=1, the flip-flop toggles. .
  The final state of Q after three pulses is 0.

A D latch samples the input D when the Enable signal goes from high to low (the latching edge). The setup time () is the minimum time the data must be stable before the latching edge. The hold time () is the minimum time the data must be stable after the latching edge.

• Latching edge occurs at ns.
• Data must be stable for ns before the edge, so it must be stable from ns.
• Data must be stable for ns after the edge, so it must be stable until ns.
  Therefore, the D input must be stable in the interval from ns to ns. The propagation delay is irrelevant for determining the required stability interval of the input D.

We use the excitation table of the SR flip-flop to match the characteristic table of the T flip-flop. The T flip-flop should hold () when T=0 and toggle () when T=1.

• When T=0, we need to hold state. For SR, this is S=0, R=0.
• When T=1 and Q=0, we need to set (Q becomes 1). For SR, this is S=1, R=0.
• When T=1 and Q=1, we need to reset (Q becomes 0). For SR, this is S=0, R=1.
  From this, we can derive the logic functions for S and R in terms of T and Q. Using a K-map or Boolean algebra, we find that and .

In a master-slave flip-flop, the master latch is active (e.g., clock HIGH), and the slave is inactive. The output of the entire flip-flop comes from the slave. When the clock becomes inactive (e.g., clock LOW), the master is disabled (frozen), and the slave becomes active, copying the master's state. Crucially, while the slave is updating its output, the master is disabled and cannot see this change. This breaks the feedback loop from the final output back to the input stage during the output transition, which is the root cause of the race-around condition.

Let's trace the state transitions. The next state is determined by the current state: , , .

• Initial State: () = 101
• After 1st Pulse: New state will be () = (1, 1, 0) -> 110
• After 2nd Pulse: New state will be () from 110 -> (0, 1, 1) -> 011
• After 3rd Pulse: New state will be () from 011 -> (1, 0, 1) -> 101
  The state returns to the initial state after 3 clock pulses. This configuration creates a state cycle of length 3: 101 -> 110 -> 011 -> 101.

The state S=1, R=1 is invalid for a standard SR flip-flop, meaning its next state is undefined or unpredictable. A D flip-flop, however, always produces a defined next state (). There is no way to map the S=1, R=1 input condition to a single value of D that replicates this undefined behavior. Any choice for D when S=R=1 (e.g., setting D=1 for a set-dominant flip-flop) is an implementation decision that changes the fundamental nature of the SR flip-flop, not a direct conversion.

The clock frequency is 50 MHz, so the clock period is ns. The rising edges of the clock occur at ns. The inputs S=1, R=0 correspond to the SET condition. The flip-flop is edge-triggered, so it will respond to the inputs at the first rising clock edge, which occurs at . The propagation delay is the time it takes for the output to change after the active clock edge. Therefore, the output Q will transition from 0 to 1 and become stable at ns.

This circuit uses an S'R' latch.

• Initial State (at A): S'=0, R'=1 -> Set state -> Q=1.
• Move to B (first contact): R'=0, S'=1 -> Reset state -> Q=0.
• Bounce back to A: S'=0, R'=1 -> Set state -> Q=1.
• Settle at B (final contact): R'=0, S'=1 -> Reset state -> Q=0.
  The SR latch effectively filters the bounces by holding its state until an opposite command is received. The final state is determined by the last contact made, which is at position B, resulting in a final state of Q=0.

Let's analyze the next state equation for this configuration: . We are given and . Substituting these into the equation gives: . The next state is always the inverse of the current state, . This is the definition of a toggle operation. The flip-flop toggles its state on every active clock edge, which means it acts as a frequency divider by 2. Therefore, the output frequency is .

Setup time is the minimum time the data input must be stable before the active clock edge. By changing D exactly on the edge, this requirement is violated. The master latch, which samples the data on the rising edge, does not have a stable input to read. Its internal nodes may not settle to a valid logic level (0 or 1) before it is disabled by the clock going low. This unresolved state is called metastability. The slave latch will then copy this metastable state, causing the final output Q to also be metastable for an indeterminate amount of time before eventually settling to a random 0 or 1.

An edge-triggered D flip-flop samples its D input at the active clock edge, but it also requires the input to remain stable for a short period after the edge, known as the hold time (). The conversion logic means that when Q changes after a propagation delay from the clock edge, the D input will also change. If this change propagates through the XOR gate and reaches the D input before the hold time has elapsed, the flip-flop's internal latch may capture an incorrect or intermediate value, leading to erroneous operation.

We want the T flip-flop to behave like a D flip-flop. The characteristic equation of a D flip-flop is . The characteristic equation of a T flip-flop is . To make them equivalent, we must have: . To find the required logic for T, we can XOR both sides with : , which simplifies to . This logic ensures the T flip-flop toggles () only when the current state Q is different from the desired next state D, and holds () when they are the same, effectively loading D into Q.

Asynchronous inputs like PRESET' and CLEAR' act independently of the clock and immediately override any synchronous operations. When CLEAR' is asserted (goes low), it forces the output Q to 0, regardless of what the J, K, and clock inputs are doing. Even though the clock edge arrives with a toggle command (J=K=1), the asynchronous CLEAR' signal takes precedence. Since the flip-flop was already at Q=0 and the CLEAR' pulse forces it to Q=0, the final state will be Q=0. The asynchronous input has ultimate control.

This describes a 2-bit synchronous counter. Since ENABLE is high, the logic is and . FF0 toggles on every clock pulse. FF1 toggles only when its input is high. Let's trace the sequence from state () = 00:

• Pulse 1 (negedge): was 0. toggles to 1. holds at 0. State: 01.
• Pulse 2 (negedge): was 1. toggles to 0. toggles to 1. State: 10.
• Pulse 3 (negedge): was 0. toggles to 1. holds at 1. State: 11.
• Pulse 4 (negedge): was 1. toggles to 0. toggles to 0. State: 00.
• The sequence is 00 -> 01 -> 10 -> 11 -> 00. The cycle length is 4. The 5th pulse will produce the same state as the 1st pulse. Therefore, the state after 5 pulses is 01.

The characteristic equation is . With and (stuck), the equation becomes . Let's analyze this:

• If T=0: . The state holds. This is correct behavior for T=0.
• If T=1: . The state is forced to 1 (SET). This is incorrect. A T flip-flop should toggle to 0 if Q was 1.
  So, the circuit can hold state when T=0, and it can be SET to 1 when T=1 (if it was 0), but it can never be CLEARED back to 0 by the T input. It can only be set.

The clock period is 20 ns. Assuming the clock starts low, the first rising edge is at t=0, and the first negative (falling) edge is at t=10 ns. The D input changes at t=8 ns. Setup time is the minimum time the input must be stable before the active clock edge. The active edge is at t=10 ns. The data is stable from t=8 ns onwards. The stability interval before the clock edge is from t=8 ns to t=10 ns, which is a duration of 2 ns. The required setup time is 3 ns. Since 2 ns < 3 ns, the setup time constraint is violated. The hold time is not violated as the data remains stable after the edge.