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Unit 4 - Practice Quiz

ECE249 50 Questions
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1 Which of the following describes a combinational logic circuit?

A. Its output depends on past and present inputs
B. Its output depends only on the present inputs
C. It contains memory elements
D. It requires a clock signal to operate

2 How many inputs and outputs does a Half Adder have?

A. 2 inputs, 1 output
B. 2 inputs, 2 outputs
C. 3 inputs, 2 outputs
D. 3 inputs, 1 output

3 What is the Boolean expression for the Sum output of a Half Adder with inputs and ?

A.
B.
C.
D.

4 What is the Boolean expression for the Carry output of a Half Adder with inputs and ?

A.
B.
C.
D.

5 A Full Adder can be implemented using:

A. Two Half Adders and an OR gate
B. Two Half Adders and an AND gate
C. One Half Adder and two OR gates
D. Two XOR gates and one AND gate

6 How many inputs are required for a Full Adder?

A. 1
B. 2
C. 3
D. 4

7 In a Full Adder with inputs , the Sum output is given by:

A.
B.
C.
D.

8 Which logic gate acts as a 1-bit comparator determining if ?

A. XOR
B. NAND
C. XNOR
D. NOR

9 The difference output () of a Half Subtractor with inputs (minuend) and (subtrahend) is:

A.
B.
C.
D.

10 The Borrow output () of a Half Subtractor () is:

A.
B.
C.
D.

11 A Multiplexer (MUX) is also known as a:

A. Data Distributor
B. Data Selector
C. Encoder
D. Decoder

12 If a Multiplexer has select lines, how many maximum data input lines can it support?

A.
B.
C.
D.

13 How many select lines are required for a 16:1 Multiplexer?

A. 2
B. 3
C. 4
D. 5

14 A 4:1 Multiplexer has inputs and select lines . What is the output when ?

A.
B.
C.
D.

15 Which combinational circuit is referred to as a 'Data Distributor'?

A. Multiplexer
B. De-multiplexer
C. Encoder
D. Full Adder

16 A 1-to-4 De-multiplexer has how many select lines?

A. 1
B. 2
C. 4
D. 0

17 A Decoder converts:

A. Non-coded information to coded form
B. Coded information to non-coded form
C. Serial data to parallel data
D. Data from one line to many lines unconditionally

18 How many output lines does a 3-to-8 line Decoder have?

A. 3
B. 8
C. 16
D. 4

19 An Encoder is a combinational circuit that has:

A. inputs and outputs
B. inputs and outputs
C. 1 input and outputs
D. inputs and 1 output

20 In a Priority Encoder:

A. All inputs must be low
B. All inputs must be high
C. If two inputs are active, the one with higher assigned priority is encoded
D. The output depends on previous state

21 Which logic gate is equivalent to a 1-bit Comparator checking for ?

A.
B.
C.
D.

22 In a 2-bit Magnitude Comparator comparing and , the condition is true if:

A. OR
B. AND
C.
D.

23 The carry output expression of a Full Adder is often simplified to:

A.
B.
C.
D.

24 Which of the following circuits is used to convert Binary to Octal?

A. Encoder
B. Decoder
C. Multiplexer
D. Comparator

25 Which of the following circuits is used to convert Decimal to BCD?

A. Decoder
B. Encoder
C. Multiplexer
D. Demultiplexer

26 To implement a Full Subtractor using Half Subtractors, you need:

A. 2 Half Subtractors and an AND gate
B. 2 Half Subtractors and an OR gate
C. 2 Half Subtractors and an XOR gate
D. 1 Half Subtractor and 1 Full Adder

27 In a 4:1 MUX, the Boolean expression for output is:

A.
B.
C.
D.

28 What happens to the unused inputs of an AND gate in a combinational circuit?

A. They should be connected to Logic 0 (Ground)
B. They should be connected to Logic 1 (VCC)
C. They should be left floating
D. They should be connected to the output

29 A 1-to-8 Demultiplexer can be implemented using:

A. A 3-to-8 Decoder with the Enable input used as the data input
B. A 4:1 Multiplexer
C. Three 2:1 Multiplexers
D. An 8-to-3 Encoder

30 Which of the following is NOT a combinational circuit?

A. Flip-Flop
B. Full Adder
C. Decoder
D. Multiplexer

31 In a 2-bit comparator comparing and , logic for occurs when:

A. OR
B. AND
C.
D. OR

32 How many 2:1 Multiplexers are required to construct a 4:1 Multiplexer?

A. 1
B. 2
C. 3
D. 4

33 The universal logic circuit that can implement any Boolean function of variables is:

A. A Multiplexer
B. A Half Adder
C. A Comparator
D. An Encoder

34 In a Full Subtractor, the 'Difference' output equation is identical to the 'Sum' output of:

A. Half Adder
B. Full Adder
C. Half Subtractor
D. Comparator

35 The minimum number of NAND gates required to implement a Half Adder is:

A. 4
B. 5
C. 9
D. 3

36 What is the function of the 'Enable' (Strobe) input on a Decoder?

A. It selects which output line is active
B. It allows the decoder to function; if disabled, all outputs are inactive
C. It acts as a clock signal
D. It reverses the output polarity

37 An Octal-to-Binary Encoder has how many inputs and outputs?

A. 8 inputs, 3 outputs
B. 3 inputs, 8 outputs
C. 8 inputs, 1 output
D. 1 input, 8 outputs

38 Which circuit is commonly used for Parallel-to-Serial conversion?

A. Decoder
B. Multiplexer
C. Demultiplexer
D. Comparator

39 What is the output of a 2-input XOR gate if both inputs are 1?

A. 1
B. 0
C. High Impedance
D. Undefined

40 In a BCD-to-7-Segment Decoder, how many outputs are there?

A. 4
B. 7
C. 10
D. 8

41 A Half Adder cannot handle:

A. Binary addition
B. Two input bits
C. Carry from a previous stage
D. Output Carry generation

42 Logic for in a 1-bit comparator is:

A.
B.
C.
D.

43 Cascading two 4-bit Full Adders enables the addition of:

A. Two 4-bit numbers
B. Two 8-bit numbers
C. Two 2-bit numbers
D. Four 1-bit numbers

44 The time required for the carry to propagate through a parallel adder is known as:

A. Hold time
B. Setup time
C. Carry propagation delay
D. Clock period

45 Which of the following describes a 1:2 De-multiplexer?

A. 1 Input, 1 Select Line, 2 Outputs
B. 2 Inputs, 1 Select Line, 1 Output
C. 1 Input, 2 Select Lines, 4 Outputs
D. 2 Inputs, 2 Select Lines, 1 Output

46 Active-LOW outputs on a decoder mean:

A. The selected output is Logic 1 (High)
B. The selected output is Logic 0 (Low) while others are High
C. The outputs are always 0
D. The outputs are high impedance

47 Which gate is best suited for parity generation and checking?

A. AND
B. NAND
C. XOR
D. OR

48 For a Full Adder, the number of combinations of inputs in the truth table is:

A. 4
B. 6
C. 8
D. 9

49 If we want to design a 1-bit full adder using a Decoder, what size Decoder is needed?

A. 2-to-4
B. 3-to-8
C. 4-to-16
D. 1-to-2

50 In a 4-to-2 Priority Encoder with inputs (where is highest priority), if , , , , what is the output code ()?

A. 00
B. 01
C. 10
D. 11
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