1Which of the following is a characteristic of a combinational logic circuit?
A.Its output depends on the present input as well as past outputs
B.Its output depends only on the present inputs
C.It requires a clock signal to operate
D.It has memory elements to store data
Correct Answer: Its output depends only on the present inputs
Explanation:A combinational logic circuit is defined by the fact that its output at any instant depends only on the present state of its inputs, having no memory or feedback loops.
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2What are the outputs of a Half Adder?
A.Sum and Difference
B.Sum and Carry
C.Difference and Borrow
D.Quotient and Remainder
Correct Answer: Sum and Carry
Explanation:A Half Adder takes two binary inputs and produces two outputs: the Sum bit and the Carry bit.
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3The logic equation for the Sum output of a Half Adder with inputs and is:
A.
B.
C.
D.
Correct Answer:
Explanation:The Sum output of a half adder is 1 when the inputs are different (0,1 or 1,0), which corresponds to the XOR operation ().
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4The logic equation for the Carry output of a Half Adder with inputs and is:
A.
B.
C.
D.
Correct Answer:
Explanation:The Carry output of a half adder is 1 only when both inputs are 1, which corresponds to the AND operation ().
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5How many inputs does a Full Adder have?
A.1
B.2
C.3
D.4
Correct Answer: 3
Explanation:A Full Adder accepts three inputs: two operand bits () and an input carry bit () from a previous stage.
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6A Full Adder can be implemented using:
A.Two Half Adders and one OR gate
B.Two Half Adders and one AND gate
C.One Half Adder and two OR gates
D.Two OR gates and two AND gates
Correct Answer: Two Half Adders and one OR gate
Explanation:Conceptually and practically, a Full Adder can be constructed by cascading two Half Adders and using an OR gate to combine the carry outputs.
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7What is the Boolean expression for the Sum () of a Full Adder with inputs ?
A.
B.
C.
D.
Correct Answer:
Explanation:The Sum bit of a Full Adder is the result of the XOR operation of all three input bits.
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8The Carry output () of a Full Adder is 1 when:
A.Only one input is high
B.Two or more inputs are high
C.All inputs are low
D.Only the carry input is high
Correct Answer: Two or more inputs are high
Explanation:The carry output is high if the majority of the inputs (2 or 3) are high. The equation is .
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9Which logic gate is exclusively used to determine the Difference in a Half Subtractor?
A.AND gate
B.OR gate
C.XOR gate
D.NAND gate
Correct Answer: XOR gate
Explanation:Similar to the Sum in an adder, the Difference in a subtractor is the result of , which logic-wise for 1 bit matches the XOR truth table ().
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10The Boolean expression for the Borrow output () of a Half Subtractor (computing ) is:
A.
B.
C.
D.
Correct Answer:
Explanation:A borrow is required only when we subtract a 1 from a 0 (). Thus, the expression is .
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11How many outputs does a Full Subtractor have?
A.1
B.2
C.3
D.4
Correct Answer: 2
Explanation:A Full Subtractor produces two outputs: Difference () and Borrow Out ().
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12In a 4-bit parallel adder (Ripple Carry Adder), the carry output of the second full adder is connected to:
A.The sum input of the third full adder
B.The carry input of the third full adder
C.The carry input of the first full adder
D.The output of the fourth full adder
Correct Answer: The carry input of the third full adder
Explanation:In a ripple carry adder, the carry out of stage becomes the carry in for stage .
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13A Multiplexer (MUX) is also known as a:
A.Data Distributor
B.Data Selector
C.Decoder
D.Encoder
Correct Answer: Data Selector
Explanation:A Multiplexer selects one of several input signals and forwards the selected input into a single line, acting as a data selector.
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14A 4:1 Multiplexer has 4 data inputs. How many select lines does it require?
A.1
B.2
C.3
D.4
Correct Answer: 2
Explanation:The number of select lines is related to the number of inputs . For 4 inputs, , so .
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15The output of a 2:1 Multiplexer with inputs and select line is given by:
A.
B.
C.
D.
Correct Answer:
Explanation:When select line , is selected (). When , is selected (). The OR sums these conditions.
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16Which combinational circuit is known as a 'Universal Logic Circuit' because it can implement any Boolean function?
A.Decoder
B.Half Adder
C.Multiplexer
D.Encoder
Correct Answer: Multiplexer
Explanation:A Multiplexer can be configured to implement any Boolean function of variables by connecting the function's truth table values to the data inputs.
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17To implement a 16:1 Multiplexer using 4:1 Multiplexers, how many 4:1 MUXs are required?
A.4
B.5
C.8
D.16
Correct Answer: 5
Explanation:You need 4 MUXs for the first stage (handling 16 inputs) and 1 MUX in the second stage to select between the outputs of the first 4. Total = 5.
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18A De-multiplexer is a circuit with:
A.Many inputs and one output
B.One input and many outputs
C.Many inputs and many outputs
D.One input and one output
Correct Answer: One input and many outputs
Explanation:A De-multiplexer (Demux) takes a single input line and routes it to one of several digital output lines.
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19A 1:8 De-multiplexer requires how many select lines?
A.1
B.2
C.3
D.8
Correct Answer: 3
Explanation:To select one of 8 outputs (), 3 select lines are required.
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20Which circuit performs the reverse operation of a Multiplexer?
A.Encoder
B.Decoder
C.De-multiplexer
D.Comparator
Correct Answer: De-multiplexer
Explanation:A Multiplexer is many-to-one, while a De-multiplexer is one-to-many. They are functional opposites.
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21A Decoder with input lines has a maximum of how many output lines?
A.
B.
C.
D.
Correct Answer:
Explanation:A decoder decodes an -bit binary code into one of unique output lines.
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22A 3-to-8 line decoder is active high. If the input is (), which output is active?
A.
B.
C.
D.
Correct Answer:
Explanation:Binary 101 corresponds to decimal 5. Therefore, output line 5 () will be active.
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23What is the main difference between a Decoder and a De-multiplexer?
A.A decoder has a data input line, a demux does not
B.A demux acts as a decoder with the data input acting as an Enable line
C.A decoder has fewer outputs than inputs
D.There is no difference
Correct Answer: A demux acts as a decoder with the data input acting as an Enable line
Explanation:Structurally, a decoder with an Enable input acts exactly like a De-multiplexer where the Enable acts as the Data Input.
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24An Encoder is a combinational circuit that converts:
A.Binary information into non-binary form
B.Active input signal into a coded binary output
C.Serial data to parallel data
D.Data from one line to many lines
Correct Answer: Active input signal into a coded binary output
Explanation:An encoder generates a binary code corresponding to the specific active input line ( inputs to outputs).
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25In a standard 8-to-3 Encoder, if inputs and are essentially high simultaneously, what is the problem called?
A.Race condition
B.Ambiguity (invalid output)
C.Propagation delay
D.Fan-out limit
Correct Answer: Ambiguity (invalid output)
Explanation:Standard encoders cannot handle multiple active inputs simultaneously; the output becomes garbled/incorrect. This necessitates a Priority Encoder.
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26A Priority Encoder resolves the issue of multiple active inputs by:
A.Shutting down the circuit
B.Encoding only the input with the highest assigned priority
C.Encoding only the input with the lowest assigned priority
D.Randomly selecting an input
Correct Answer: Encoding only the input with the highest assigned priority
Explanation:A Priority Encoder ensures that if multiple inputs are active, only the binary code of the highest priority input is generated.
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27A Decimal-to-BCD encoder has how many inputs and outputs?
A.4 inputs, 10 outputs
B.10 inputs, 4 outputs
C.10 inputs, 10 outputs
D.8 inputs, 3 outputs
Correct Answer: 10 inputs, 4 outputs
Explanation:It takes 10 decimal inputs (0-9) and produces a 4-bit BCD output.
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28Which logic gate is primarily used to check for equality () in a 1-bit Comparator?
A.XOR
B.XNOR
C.AND
D.OR
Correct Answer: XNOR
Explanation:The XNOR gate produces a high output only when both inputs are the same (both 0 or both 1), making it the standard equality detector.
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29In a 1-bit magnitude comparator with inputs and , the logic expression for is:
A.
B.
C.
D.
Correct Answer:
Explanation: is true only when and . The minterm for this is .
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30In a 1-bit magnitude comparator with inputs and , the logic expression for is:
A.
B.
C.
D.
Correct Answer:
Explanation: is true only when and . The minterm for this is .
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31A 2-bit magnitude comparator compares two binary numbers () and (). How many outputs does it generally have?
A.1
B.2
C.3
D.4
Correct Answer: 3
Explanation:Standard comparators provide three outputs indicating the relationship between inputs: , , and .
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32For a 2-bit comparator ( and ), the condition for is:
A. OR
B. AND
C.
D.
Correct Answer: AND
Explanation:For two 2-bit numbers to be equal, their MSBs must be equal AND their LSBs must be equal.
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33If you need to subtract from using a Full Adder, what modification is needed?
A.Invert and add 1
B.Invert and set Carry Input () to 1
C.Set to 0
D.Connect inputs directly
Correct Answer: Invert and set Carry Input () to 1
Explanation:Subtraction using 2's complement involves adding the 2's complement of the subtrahend. The 2's complement of is . We invert and provide the '+1' via the carry input.
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34Which of the following is NOT a combinational circuit?
A.Multiplexer
B.Decoder
C.Flip-Flop
D.Full Adder
Correct Answer: Flip-Flop
Explanation:A Flip-Flop is a sequential circuit element because it has memory and stores state. The others are combinational.
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35In a 2:4 Decoder constructed using NAND gates (Active Low outputs), if the inputs are valid, how many outputs are LOW at any specific time?
A.
B.1
C.2
D.3
Correct Answer: 1
Explanation:For an active-low decoder, the selected output goes LOW (0), while all non-selected outputs remain HIGH (1).
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36Which circuit is commonly used to drive a Seven Segment Display?
A.Encoder
B.Decoder
C.Multiplexer
D.Comparator
Correct Answer: Decoder
Explanation:A BCD-to-7-Segment Decoder is specifically designed to convert a binary number into signals that light up the appropriate segments of the display.
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37How many NOT gates are required to build a 2:1 Multiplexer if basic gates (AND, OR, NOT) are used?
A.
B.1
C.2
D.3
Correct Answer: 1
Explanation:Only one NOT gate is required to invert the select line to get . (Though inputs might need buffering, the core logic uses 1).
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38If a Full Adder has inputs , what are the outputs?
A.
B.
C.
D.
Correct Answer:
Explanation: (decimal), which is . So, Sum=1 and Carry=1.
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39If a Half Subtractor has inputs and , what are the outputs?
A.
B.
C.
D.
Correct Answer:
Explanation: requires a borrow. Difference becomes , and Borrow is 1.
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40What is the primary disadvantage of a Ripple Carry Adder?
A.It consumes too much power
B.It requires too many gates
C.High propagation delay
D.It cannot perform subtraction
Correct Answer: High propagation delay
Explanation:The carry must propagate through every full adder stage from LSB to MSB, causing a delay proportional to the number of bits.
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41To expand a 2-bit comparator to a 4-bit comparator, one effectively connects the outputs of the lower bits to the:
A.Input stage of the higher bits
B.Cascading inputs of the higher bit comparator
C.Output of the higher bits
D.Power supply
Correct Answer: Cascading inputs of the higher bit comparator
Explanation:Comparators often have cascading inputs () to allow linking multiple units to compare larger numbers.
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42What is the relationship between the Enable input of a Decoder and the operation of the circuit?
A.It selects the output line
B.It determines if the circuit is active or disabled
C.It inverts the output
D.It serves as the MSB of the input
Correct Answer: It determines if the circuit is active or disabled
Explanation:The Enable pin allows the decoder to be turned on or off. If disabled, no outputs are active regardless of data inputs.
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43A keyboard encoder typically uses which type of encoding logic?
A.Sequential Encoding
B.Priority Encoding
C.Ripple Encoding
D.Differential Encoding
Correct Answer: Priority Encoding
Explanation:Keyboards use priority encoders to handle cases where two keys are pressed simultaneously; usually, the key with the higher definition/position is registered.
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44Which circuit allows a single data line to control multiple devices addressed by a select code?
A.Multiplexer
B.De-multiplexer
C.Encoder
D.Adder
Correct Answer: De-multiplexer
Explanation:A De-multiplexer routes the single data line to one of many specific destinations based on the address (select) code.
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45The Look-Ahead Carry Adder is designed to overcome which limitation?
A.Power consumption of Full Adders
B.Propagation delay of Ripple Carry Adders
C.Complexity of Half Adders
D.Number of inputs limited to 2
Correct Answer: Propagation delay of Ripple Carry Adders
Explanation:Look-Ahead Carry logic calculates carry bits in parallel based on inputs, eliminating the 'ripple' delay.
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46In a 2-bit Comparator comparing and , when is true?
A.If OR ( AND )
B.If AND
C.If
D.If AND
Correct Answer: If OR ( AND )
Explanation:MSB has priority. If MSB , then . If MSBs are equal, we check the LSBs ().
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47How many 2-input NAND gates are required to implement a Half Adder?
A.3
B.4
C.5
D.9
Correct Answer: 5
Explanation:A standard XOR implementation takes 4 NAND gates. The Carry is an AND gate, which can be derived from the intermediate steps of the XOR construction, totaling 5 NAND gates for the whole HA.
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48The inputs to a 2:4 Decoder are and . Which output corresponds to the minterm ?
A.
B.
C.
D.
Correct Answer:
Explanation:Minterm corresponds to binary 11 (decimal 3). Thus inputs select this output.
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49If we connect the data inputs of a 4:1 MUX as: , what logic gate does this MUX simulate (Select lines A, B)?
A.AND
B.OR
C.XOR
D.NAND
Correct Answer: XOR
Explanation:The output is 1 when select lines are 01 or 10. This is the truth table for XOR ().
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50A Full Subtractor logic circuit typically requires:
A.Two Half Subtractors and an OR gate
B.Two Half Subtractors and an AND gate
C.Two Half Subtractors and an XOR gate
D.One Half Subtractor and one Half Adder
Correct Answer: Two Half Subtractors and an OR gate
Explanation:Similar to the Full Adder, a Full Subtractor is constructed by cascading two Half Subtractors and using an OR gate to combine the borrow outputs.
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