Unit5 - Subjective Questions
ECE249 • Practice Questions with Detailed Answers
Differentiate between Combinational and Sequential Logic Circuits.
The differences between Combinational and Sequential Logic Circuits are detailed below:
| Feature | Combinational Logic Circuits | Sequential Logic Circuits |
|---|---|---|
| Output Dependency | Output depends only on the present input. | Output depends on present input and past output (history). |
| Memory | Does not require memory elements. | Requires memory elements (Flip-Flops/Latches) to store state. |
| Feedback | No feedback path exists. | Feedback path exists from output to input. |
| Clock | Clock signal is not required. | Triggered by a clock signal (except asynchronous latches). |
| Design Complexity | Generally simpler to design. | More complex due to timing and state issues. |
| Examples | Adders, Multiplexers, Encoders, Decoders. | Flip-Flops, Registers, Counters. |
Explain the operation of an SR Latch using NAND gates with the help of a truth table.
An SR (Set-Reset) Latch using NAND gates is an active-low input device. It consists of two cross-coupled NAND gates.
Logic Diagram:
It has two inputs, (Set) and (Reset), and two outputs, and .
Operation:
- (No Change): The latch remains in its previous state ().
- (Set State): The output becomes 1.
- (Reset State): The output becomes 0.
- (Invalid/Forbidden): Both outputs try to go High, which violates the logic that and must be complements. This state is avoided.
Truth Table:
| State | |||
|---|---|---|---|
| 1 | 1 | No Change | |
| 0 | 1 | 1 | Set |
| 1 | 0 | 0 | Reset |
| 0 | 0 | ? | Invalid |
Distinguish between a Latch and a Flip-Flop.
Latch vs. Flip-Flop:
-
Triggering Method:
- Latch: It is level-triggered. It changes output state as long as the enable input is active (High or Low level).
- Flip-Flop: It is edge-triggered. It changes output state only at the transitions of the clock signal (Positive or Negative edge).
-
Synchronicity:
- Latch: Often considered asynchronous (unless gated), responding immediately to changes in inputs while enabled.
- Flip-Flop: Synchronous device, operating in sync with the clock frequency.
-
Design Complexity:
- Latch: Basic building block, simpler circuit.
- Flip-Flop: Usually constructed using two latches (Master-Slave configuration) or complex gating logic to detect edges.
-
Symbol:
- Latches usually show Enable ( or ) inputs, while Flip-Flops show a Clock triangle symbol () on the control input.
Explain the working of a clocked SR Flip-Flop. Derive its characteristic equation.
Clocked SR Flip-Flop:
An SR Flip-Flop has two data inputs (S and R) and a clock input (CLK).
Operation:
- S=0, R=0: No change in state ().
- S=0, R=1: Resets the output ().
- S=1, R=0: Sets the output ().
- S=1, R=1: Invalid/Indeterminate state.
Characteristic Table:
| S | R | ||
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | X | X |
Derivation of Characteristic Equation:
Using a K-Map for :
- Grouping the 1s results in terms and .
Equation:
Describe the operation of a JK Flip-Flop and explain how it overcomes the limitation of the SR Flip-Flop.
JK Flip-Flop:
The JK Flip-Flop is a modification of the SR Flip-Flop. It overcomes the indeterminate state occurring when and .
Logic Construction:
Inputs (Set equivalent) and (Reset equivalent) are fed into AND gates along with the feedback from outputs and .
- is ANDed with .
- is ANDed with .
Operation Modes:
- J=0, K=0 (No Change): Holds the current state.
- J=0, K=1 (Reset): Forces .
- J=1, K=0 (Set): Forces .
- J=1, K=1 (Toggle): This is the key difference. Instead of being invalid, the output complements the previous state ().
Characteristic Equation:
What is the 'Race Around Condition' in JK Flip-Flops? How can it be avoided?
Race Around Condition:
In a level-triggered JK Flip-Flop, if , (Toggle mode) and the clock pulse width () is longer than the propagation delay of the Flip-Flop gates (), the output will toggle multiple times within a single clock pulse.
- Condition: .
- This causes an uncertain state at the end of the clock pulse, known as the Race Around Condition.
Methods to Avoid:
- Edge Triggering: Using edge-triggered Flip-Flops which are sensitive only to transitions, not the duration of the level.
- Master-Slave Configuration: Using a Master-Slave JK Flip-Flop where the master changes on the leading edge and the slave updates on the trailing edge.
- Delay Lines: Intentionally increasing propagation delay such that (less practical).
Explain the detailed working of a Master-Slave JK Flip-Flop with a logic diagram.
Master-Slave JK Flip-Flop:
This circuit consists of two JK Flip-Flops connected in a cascade arrangement. The first is called the Master and the second is the Slave.
Construction:
- Master: Driven by the Clock (CLK). Inputs are J and K.
- Slave: Driven by the inverted Clock (). Inputs are the outputs of the Master.
Working:
-
When Clock is HIGH (1):
- The Master is active and processes inputs J and K.
- The Slave is inactive (isolated) because its clock is LOW.
- The output of the Master is set but not yet seen at the final output.
-
When Clock goes LOW (1 to 0 transition):
- The Master becomes inactive and holds its data.
- The Slave becomes active (clock input becomes HIGH).
- The Slave reads the output of the Master and transfers it to the final output .
Significance:
Since the output changes only at the falling edge of the clock, the feedback path cannot change the input during the same clock cycle, effectively eliminating the Race Around Condition.
Describe the D Flip-Flop. Derive its characteristic equation and truth table.
D (Data or Delay) Flip-Flop:
The D Flip-Flop has a single data input . It is constructed from an SR or JK Flip-Flop by ensuring inputs are complements ( or ).
Operation:
It transfers the data present at input to the output at the active edge of the clock.
- If , becomes 1 (Set).
- If , becomes 0 (Reset).
Truth Table:
| Clock | D | |
|---|---|---|
| 0 | 0 | |
| 1 | 1 |
Characteristic Equation:
Based on the characteristic table (where Next State follows input D irrespective of Present State):
Explain the T (Toggle) Flip-Flop and its application.
T (Toggle) Flip-Flop:
A T Flip-Flop has a single input . It is usually derived from a JK Flip-Flop by connecting and inputs together ().
Operation:
- T = 0: . The Flip-Flop remains in the No Change state ().
- T = 1: . The Flip-Flop acts in Toggle mode. The output complements the previous state ().
Characteristic Equation:
Applications:
- Frequency Division: The output frequency is half the input clock frequency when .
- Binary Counters: Essential component in designing binary counters.
Write down the Excitation Tables for SR, JK, D, and T Flip-Flops.
An Excitation Table lists the required inputs to achieve a specific transition from Present State () to Next State ().
| 1. SR Flip-Flop: | S | R | ||
|---|---|---|---|---|
| 0 | 0 | 0 | X | |
| 0 | 1 | 1 | 0 | |
| 1 | 0 | 0 | 1 | |
| 1 | 1 | X | 0 |
| 2. JK Flip-Flop: | J | K | ||
|---|---|---|---|---|
| 0 | 0 | 0 | X | |
| 0 | 1 | 1 | X | |
| 1 | 0 | X | 1 | |
| 1 | 1 | X | 0 |
| 3. D Flip-Flop: | D | ||
|---|---|---|---|
| 0 | 0 | 0 | |
| 0 | 1 | 1 | |
| 1 | 0 | 0 | |
| 1 | 1 | 1 |
| 4. T Flip-Flop: | T | ||
|---|---|---|---|
| 0 | 0 | 0 | |
| 0 | 1 | 1 | |
| 1 | 0 | 1 | |
| 1 | 1 | 0 |
Explain the general procedure for converting one type of Flip-Flop into another.
The conversion of a flip-flop involves designing a combinational circuit that drives the inputs of the Available Flip-Flop to behave like the Required Flip-Flop.
Procedure Steps:
- Identify Flip-Flops: Determine the Required Flip-Flop (whose characteristics we want) and the Available Flip-Flop (the actual hardware).
- Characteristic Table: Write the Characteristic Table of the Required Flip-Flop.
- Excitation Table: Append the excitation requirements of the Available Flip-Flop to the table. This links the Next State () to the inputs of the available Flip-Flop.
- K-Map Simplification: Draw K-Maps for the inputs of the Available Flip-Flop in terms of the Required Flip-Flop's inputs and Current State ().
- Logic Diagram: Draw the logic circuit using gates derived from the K-Map expressions connected to the Available Flip-Flop.
Convert an SR Flip-Flop into a JK Flip-Flop.
To convert SR (Available) to JK (Required):
1. Truth Table Creation:
Use JK inputs and determine required S and R values based on JK transitions.
| J | K | (Req) | S (Excitation) | R (Excitation) | |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | X |
| 0 | 0 | 1 | 1 | X | 0 |
| 0 | 1 | 0 | 0 | 0 | X |
| 0 | 1 | 1 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 | X | 0 |
| 1 | 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 |
2. K-Map Simplification:
- For S: Grouping yields
- For R: Grouping yields
3. Realization:
Connect and to an AND gate feeding . Connect and to an AND gate feeding .
Convert a JK Flip-Flop into a D Flip-Flop.
Goal: Make a JK Flip-Flop behave like a D Flip-Flop.
- Required: D Flip-Flop ()
- Available: JK Flip-Flop
Logic Derivation:
We need to find inputs and in terms of .
| D | J (Req) | K (Req) | ||
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | X |
| 0 | 1 | 0 | X | 1 |
| 1 | 0 | 1 | 1 | X |
| 1 | 1 | 1 | X | 0 |
K-Map:
- For J: From the table, when , . .
- For K: From the table, when , . .
Circuit:
Connect input directly to . Connect through a NOT gate to . This creates a standard D Flip-Flop implementation.
Perform the conversion of a JK Flip-Flop to a T Flip-Flop.
Goal: Realize T Flip-Flop functionality using a JK Flip-Flop.
Analysis:
- T Flip-Flop Logic: No Change; Toggle.
- JK Flip-Flop Logic: No Change; Toggle.
Mapping:
Looking at the requirements:
- When , we need .
- When , we need .
Result:
Circuit:
Connect the input to both and inputs of the JK Flip-Flop.
Convert a D Flip-Flop into a T Flip-Flop.
Goal: Use a D Flip-Flop to emulate a T Flip-Flop.
- Available: D Flip-Flop ()
- Required: T Flip-Flop ()
Derivation:
Since for a D Flip-Flop, the next state is exactly the input D (), we simply need to drive the D input with the characteristic equation of the T Flip-Flop.
Characteristic Equation of T FF:
Mapping:
Therefore, we set:
Circuit Implementation:
Use an XOR gate. Inputs to the XOR gate are and the feedback . The output of the XOR gate is connected to the input.
Describe the function of Preset (Pr) and Clear (Clr) inputs in a Flip-Flop.
Preset and Clear are asynchronous inputs (or override inputs) found on standard Flip-Flop ICs.
-
Functionality:
- They operate independently of the Clock and the synchronous data inputs (J, K, D, S, R).
- They represent direct paths to set or reset the latching element inside.
-
Preset (Pr / ):
- Used to set the Flip-Flop state to High () immediately.
- Usually Active Low. If , is forced to 1.
-
Clear (Clr / ):
- Used to reset the Flip-Flop state to Low () immediately.
- Usually Active Low. If , is forced to 0.
Usage: Used for initializing systems (Power-on Reset) to a known state before normal clocked operation begins.
Compare Level Triggering and Edge Triggering.
Comparison of Triggering Methods:
| Feature | Level Triggering | Edge Triggering |
|---|---|---|
| Definition | The circuit responds to inputs when the clock is at a specific logic level (High or Low). | The circuit responds to inputs only at the transition of the clock signal (Rising or Falling edge). |
| Active Duration | Active for the entire duration of the pulse width (). | Active only for a momentary instant of transition. |
| Device Type | Used in Latches. | Used in Flip-Flops. |
| Sensitivity | Sensitive to input glitches/noise while the clock is active. | Less sensitive to noise; inputs are sampled only at the edge. |
| Issues | Susceptible to Race Around condition (in JK). | Eliminates Race Around condition in feedback circuits. |
Convert an SR Flip-Flop to a D Flip-Flop.
Goal: Configure SR to work as D.
- Required: D Flip-Flop logic.
- Available: SR Flip-Flop.
Truth Table Analysis:
- D FF: Input 0 Output 0. Input 1 Output 1.
- SR FF: To get Output 0, we need . To get Output 1, we need .
Mapping:
- When : Set .
- When : Set .
Equations:
Implementation:
Connect input to . Connect through a NOT gate to .
Convert a D Flip-Flop into an SR Flip-Flop.
Goal: Use a D Flip-Flop to emulate an SR Flip-Flop.
- Available: D Flip-Flop ()
- Required: SR Flip-Flop ()
Analysis:
The Next State equation for the D Flip-Flop is simply .
The Next State equation for the SR Flip-Flop is .
Mapping:
To make the D Flip-Flop behave like an SR, we must drive the D input with the SR characteristic logic:
Circuit:
- AND gate: Inputs (inverted R) and .
- OR gate: Inputs and the output of the AND gate.
- Output of OR gate connects to the input.
Derive the characteristic equation of a T Flip-Flop using its truth table and K-Map.
Step 1: Characteristic Table of T Flip-Flop
| T | ||
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Step 2: K-Map for
We map the output based on inputs and .
- Cell (T=0, Q=0): 0
- Cell (T=0, Q=1): 1
- Cell (T=1, Q=0): 1
- Cell (T=1, Q=1): 0
This checkerboard pattern represents the Exclusive-OR (XOR) function.
Step 3: Equation Derivation