1What is the basic building block of a digital register?
A.Logic Gate
B.Flip-Flop
C.Multiplexer
D.Decoder
Correct Answer: Flip-Flop
Explanation:A register is a group of flip-flops used to store or shift binary data. Each flip-flop stores one bit of information.
Incorrect! Try again.
2In a 4-bit Serial-In Serial-Out (SISO) shift register, how many clock pulses are required to load a 4-bit number?
A.1
B.2
C.4
D.8
Correct Answer: 4
Explanation:In a SISO register, data enters one bit at a time per clock cycle. To load bits, it takes clock pulses.
Incorrect! Try again.
3Which type of shift register is the fastest for loading and retrieving data?
A.SISO (Serial-In Serial-Out)
B.SIPO (Serial-In Parallel-Out)
C.PISO (Parallel-In Serial-Out)
D.PIPO (Parallel-In Parallel-Out)
Correct Answer: PIPO (Parallel-In Parallel-Out)
Explanation:PIPO registers load all bits simultaneously (parallel) and output all bits simultaneously, requiring only 1 clock pulse for loading, making them the fastest.
Incorrect! Try again.
4If the content of a 4-bit shift register is $1011$, what is the content after shifting it one position to the right (assuming serial input is 0)?
A.1101
B.0101
C.0111
D.1010
Correct Answer: 0101
Explanation:Shifting $1011$ to the right with a 0 input results in the LSB ($1$) being lost and a $0$ entering the MSB position. The result is $0101$.
Incorrect! Try again.
5A Universal Shift Register is a register that has:
A.Only serial input and output capability
B.Only parallel input and output capability
C.Both serial and parallel input/output capability, and bidirectional shifting
D.The ability to count in binary
Correct Answer: Both serial and parallel input/output capability, and bidirectional shifting
Explanation:A Universal Shift Register can perform all register operations: SISO, SIPO, PISO, PIPO, and can shift data both left and right.
Incorrect! Try again.
6In a Serial-In Parallel-Out (SIPO) shift register with stages, how many clock pulses are needed to convert serial data to parallel output?
A.1
B.N
C.N-1
D.2N
Correct Answer: N
Explanation:It takes clock pulses to shift all bits into the register. Once loaded, the parallel output is available immediately.
Incorrect! Try again.
7Which application is a PISO (Parallel-In Serial-Out) register most commonly used for?
A.Parallel data storage
B.Converting parallel data to serial for transmission
C.Frequency division
D.Digital clock generation
Correct Answer: Converting parallel data to serial for transmission
Explanation:PISO registers are essential in communication systems to convert parallel data from a computer bus into a serial stream for transmission over a single wire.
Incorrect! Try again.
8What happens to the data stored in a shift register when the power is turned off?
A.It shifts to the right
B.It shifts to the left
C.It is retained indefinitely
D.It is lost
Correct Answer: It is lost
Explanation:Shift registers are constructed using flip-flops (typically D or J-K), which are volatile memory elements. Data is lost upon power loss.
Incorrect! Try again.
9To effect a 'multiplication by 2' operation on a binary number stored in a register, one must:
A.Shift data to the right
B.Shift data to the left
C.Invert the data
D.Load the data in parallel
Correct Answer: Shift data to the left
Explanation:In binary arithmetic, shifting bits to the left adds a zero to the LSB, effectively multiplying the value by 2 (e.g., becomes ).
Incorrect! Try again.
10How many flip-flops are required to construct a Mod-12 counter?
A.3
B.4
C.12
D.6
Correct Answer: 4
Explanation:The number of flip-flops must satisfy . For Mod-12, (too small) and (sufficient). Therefore, 4 flip-flops are needed.
Incorrect! Try again.
11An Asynchronous counter is also known as a:
A.Ripple Counter
B.Parallel Counter
C.Decade Counter
D.Ring Counter
Correct Answer: Ripple Counter
Explanation:It is called a Ripple Counter because the clock pulse triggers the first flip-flop, and its output triggers the second, causing the state change to 'ripple' through the chain.
Incorrect! Try again.
12In a 4-bit Asynchronous Down Counter using negative edge-triggered flip-flops, the clock input of the next stage is connected to:
A.The output of the previous stage
B.The output of the previous stage
C.The main clock source
D.The Clear input
Correct Answer: The output of the previous stage
Explanation:For a Down counter using negative edge-triggered flip-flops, the clock of the next stage should be driven by the output of the previous stage (or to drive an Up counter).
Incorrect! Try again.
13What is the primary disadvantage of an Asynchronous counter compared to a Synchronous counter?
Explanation:In asynchronous counters, delays add up because each flip-flop waits for the previous one to toggle. This limits the maximum operating frequency.
Incorrect! Try again.
14In a Synchronous counter, the clock input of all flip-flops is connected:
A.To the output of the previous flip-flop
B.To a common clock signal
C.To the input of the next flip-flop
D.Randomly
Correct Answer: To a common clock signal
Explanation:Synchronous counters are defined by all flip-flops being triggered simultaneously by the same master clock signal.
Incorrect! Try again.
15A Mod-N counter divides the input frequency by:
A.N
B.
C.
D.
Correct Answer: N
Explanation:A Mod-N counter cycles through states before repeating. Therefore, the frequency of the MSB output is .
Incorrect! Try again.
16Which logic gate is typically required to implement a Synchronous counter to determine the next state?
A.NOT gates only
B.AND gates
C.Inverters only
D.Buffers
Correct Answer: AND gates
Explanation:AND gates are used to decode the states of previous flip-flops to control the inputs (J, K or T, D) of the subsequent flip-flops in a synchronous design.
Incorrect! Try again.
17A 3-bit binary counter counts through how many natural states?
A.3
B.6
C.8
D.9
Correct Answer: 8
Explanation:A 3-bit counter has distinct states, ranging from $000$ to $111$.
Incorrect! Try again.
18To construct a BCD (Decade) counter from a 4-bit binary counter, the counter is reset after reaching which binary count?
A.1001 ()
B.1010 ()
C.1111 ()
D.1000 ()
Correct Answer: 1001 ()
Explanation:A BCD counter counts 0-9. It must operate normally up to 9 ($1001$). The next state ($1010$) is usually detected to trigger a reset, effectively cycling 0-9. (Note: Depending on design, the reset triggers on 1010 to force 0000).
Incorrect! Try again.
19What is the maximum count of a 5-bit binary counter?
A.15
B.31
C.32
D.64
Correct Answer: 31
Explanation:The maximum decimal value a binary counter can represent is . For , .
Incorrect! Try again.
20If an Asynchronous counter uses flip-flops with a propagation delay of each, what is the total propagation delay for a 4-bit ripple counter?
A.
B.
C.
D.
Correct Answer:
Explanation:In a ripple counter, delays are cumulative. .
Incorrect! Try again.
21A Ring Counter consisting of 5 Flip-Flops will have how many states?
A.5
B.10
C.32
D.25
Correct Answer: 5
Explanation:A standard Ring Counter with flip-flops has exactly valid states (a circulating '1').
Incorrect! Try again.
22A Johnson Ring Counter with flip-flops has a modulus of:
A.N
B.2N
C.
D.
Correct Answer: 2N
Explanation:A Johnson counter (twisted ring counter) doubles the number of states compared to a standard ring counter, providing states.
Incorrect! Try again.
23Which of the following describes the feedback mechanism in a standard Ring Counter?
A.Output of the last FF () connected to Input of the first FF ()
B.Inverted Output of the last FF () connected to Input of the first FF ()
C.Output of the last FF connected to the Clock
D.Output of the first FF connected to the Input of the last FF
Correct Answer: Output of the last FF () connected to Input of the first FF ()
Explanation:A standard Ring Counter circulates the bit by feeding the non-inverted output () of the last stage back to the input of the first stage.
Incorrect! Try again.
24Which of the following describes the feedback mechanism in a Johnson Counter?
A.Output of the last FF () connected to Input of the first FF ()
B.Inverted Output of the last FF () connected to Input of the first FF ()
C.External clock connected to data input
D.No feedback is used
Correct Answer: Inverted Output of the last FF () connected to Input of the first FF ()
Explanation:A Johnson counter connects the inverted output () of the last flip-flop to the input of the first, creating a twisted ring effect.
Explanation:This sequence shows 1s filling up from the left and then 0s filling up from the left, which is characteristic of a Johnson counter sequence.
Incorrect! Try again.
26One disadvantage of a basic Ring Counter is:
A.It is very slow
B.It is not self-starting
C.It requires complex decoding
D.It uses too few flip-flops
Correct Answer: It is not self-starting
Explanation:If a Ring Counter enters an unused state (e.g., due to noise), it may stay in an invalid loop and not return to the valid sequence without additional logic.
Incorrect! Try again.
27Which counter type typically requires the least decoding logic to detect specific states?
A.Binary Counter
B.Ring Counter
C.Johnson Counter
D.Ripple Counter
Correct Answer: Ring Counter
Explanation:In a Ring Counter, only one flip-flop is high at a time. Therefore, no logic gates are needed to decode a state; the output of the flip-flop itself indicates the state.
Incorrect! Try again.
28For a Mod-16 counter, how many unused states are there if implemented using a Johnson Counter configuration?
A.0
B.8
C.240
D.Unused states depends on the number of flip flops
Correct Answer: 240
Explanation:Wait, let's re-evaluate. To get Mod-16 using Johnson, we need FFs. Total states for 8 FFs is . Valid states = 16. Unused = .
Incorrect! Try again.
29In a 4-bit Ring Counter, if the initial state is $1000$, what is the state after 2 clock pulses?
30Which flip-flop type is most commonly used to design counters due to its toggle capability?
A.D Flip-Flop
B.RS Flip-Flop
C.T Flip-Flop
D.Latch
Correct Answer: T Flip-Flop
Explanation:T (Toggle) Flip-Flops are ideal for counters because holding the input High causes the output to toggle on every clock edge, which is the basis of binary counting.
Incorrect! Try again.
31What is the phenomenon called where the output of a counter momentarily assumes an incorrect state due to propagation delays?
A.Aliasing
B.Glitch
C.Drift
D.Hysteresis
Correct Answer: Glitch
Explanation:Glitches (or decoding spikes) occur in asynchronous counters because flip-flops change states at slightly different times due to accumulated delays.
Incorrect! Try again.
32To design a Synchronous Up/Down counter, what additional signal is required?
A.A Mode Control input (M)
B.A faster clock
C.More Flip-Flops
D.A second power supply
Correct Answer: A Mode Control input (M)
Explanation:A control line (often labeled M or Up/Down) determines whether the logic gates driving the flip-flops implement the 'Up' counting logic or 'Down' counting logic.
Incorrect! Try again.
33The master reset input in most counters is usually:
A.Synchronous
B.Asynchronous
C.Dependent on the D input
D.Unused
Correct Answer: Asynchronous
Explanation:Master Reset (Clear) inputs usually override the clock and inputs immediately to set the counter to zero, making them Asynchronous.
Incorrect! Try again.
34A Mod-10 synchronous counter is designed using J-K flip-flops. What is the state of the J and K inputs for the unused states?
A.Fixed to 0
B.Fixed to 1
C.Don't Care ()
D.Inverted
Correct Answer: Don't Care ()
Explanation:When designing using Karnaugh maps, unused states are treated as 'Don't Care' conditions to simplify the boolean expressions for the J and K inputs.
Incorrect! Try again.
35If the input frequency to a 4-bit ripple counter is , what is the frequency at the output of the MSB?
A.
B.
C.
D.
Correct Answer:
Explanation:A 4-bit counter is a Mod-16 counter (). .
Incorrect! Try again.
36Which of the following counters is a 'weighted' code counter?
A.Ring Counter
B.Johnson Counter
C.Binary Counter
D.Walking One Counter
Correct Answer: Binary Counter
Explanation:In a standard Binary Counter, each bit position has a specific weight ($1, 2, 4, 8...$). Ring and Johnson counters use unweighted codes.
Incorrect! Try again.
37How many clock pulses are required to load 4 bits of data into a PIPO register?
A.0
B.1
C.2
D.4
Correct Answer: 1
Explanation:Parallel-In Parallel-Out registers load data on a single clock edge.
Incorrect! Try again.
38Which register type acts as a buffer or temporary storage?
A.SISO
B.PIPO
C.Ring Counter
D.Ripple Counter
Correct Answer: PIPO
Explanation:PIPO registers are often used as latches or buffers to hold data stable for the next stage of processing.
Incorrect! Try again.
39In a 4-bit Johnson counter, the decoding gate to detect the state $0001$ would be:
A.2-input AND gate
B.4-input AND gate
C.OR gate
D.NOT gate
Correct Answer: 2-input AND gate
Explanation:Johnson counter states can be uniquely identified using only 2 inputs. For a 4-bit sequence, adjacent 0/1 transitions identify the state uniquely.
Incorrect! Try again.
40Which of the following is true for a Synchronous Counter?
A.Slower than Asynchronous Counter
B.Requires less hardware than Asynchronous Counter
C.No cumulative propagation delay
D.Clock is applied only to the LSB
Correct Answer: No cumulative propagation delay
Explanation:Since all flip-flops trigger at the same time, the delay is essentially that of a single flip-flop (plus gate delay), rather than the sum of all flip-flops.
Incorrect! Try again.
41If a counter counts from $000$ to $101$ and then resets, it is a:
A.Mod-5 Counter
B.Mod-6 Counter
C.Mod-8 Counter
D.Mod-4 Counter
Correct Answer: Mod-6 Counter
Explanation:The states are 0, 1, 2, 3, 4, 5. There are 6 distinct states. Therefore, it is a Mod-6 counter.
Incorrect! Try again.
42Which statement is true regarding the initialization of a standard Ring Counter?
A.It must be reset to all 0s
B.It must be preset with a single 1 (e.g., $1000$)
C.It must be preset to all 1s
D.Initialization is not required
Correct Answer: It must be preset with a single 1 (e.g., $1000$)
Explanation:For a Ring Counter to function as a circulating register, it requires a single '1' to be pre-loaded. All 0s would result in a static 0 output.
Incorrect! Try again.
43What is the equivalent decimal value of the highest state in a Mod-16 counter?
A.16
B.15
C.1
D.32
Correct Answer: 15
Explanation:A Mod-16 counter counts from 0 to 15.
Incorrect! Try again.
44The time delay generated by an -bit SISO shift register with clock frequency is:
A.
B.
C.
D.
Correct Answer:
Explanation:Each stage adds one clock period delay . For stages, total delay is .
Incorrect! Try again.
45Which device is used to parallel load a shift register asynchronously?
A.The Clock input
B.The Preset and Clear inputs
C.The J and K inputs
D.The Q output
Correct Answer: The Preset and Clear inputs
Explanation:Preset (PRE) and Clear (CLR) are asynchronous inputs that can force the flip-flops to 1 or 0 immediately, allowing for parallel loading regardless of the clock.
Incorrect! Try again.
46A 3-bit down counter is at state $000$. After one clock pulse, the state will be:
A.001
B.111
C.110
D.100
Correct Answer: 111
Explanation:In a binary down counter, decremented 0 rolls over to the maximum value. (decimal 7).
Incorrect! Try again.
47Which counter configuration can be used to generate multiphase clock signals?
A.Ripple Counter
B.Ring Counter
C.Up/Down Counter
D.Mod-10 Counter
Correct Answer: Ring Counter
Explanation:A Ring Counter produces a sequence of non-overlapping pulses (one-hot), effectively creating multiphase clocks useful for timing control sequences.
Incorrect! Try again.
48How does a 'Locked-out' condition occur in a counter?
A.When the power supply is too low
B.When the counter enters an unused state and cannot return to a valid sequence
C.When the clock frequency is too high
D.When the reset button is pressed
Correct Answer: When the counter enters an unused state and cannot return to a valid sequence
Explanation:In counters where , unused states exist. If noise forces the counter into an unused state and the next-state logic loops within unused states, it is locked out.
Incorrect! Try again.
49What is the minimum number of flip-flops required to generate a sequence: $0, 1, 3, 2, 6, 7, 5, 4$ and repeat?
A.2
B.3
C.4
D.8
Correct Answer: 3
Explanation:The highest number in the sequence is 7 (), which requires 3 bits. There are 8 unique states (), so 3 flip-flops are sufficient.
Incorrect! Try again.
50In a 4-bit Asynchronous Up Counter, if the clock frequency is , the frequency at the output of the second flip-flop (Q1) is:
A.
B.
C.
D.
Correct Answer:
Explanation:Q0 is . Q1 (the second flip-flop) divides Q0 by 2, resulting in .