Unit5 - Subjective Questions

Definition:
A Shift Register is a sequential logic circuit composed of a cascade of flip-flops (usually D flip-flops) capable of storing and shifting binary data. It allows data to move from one stage to the next with each clock pulse.

Modes of Operation:
Shift registers are classified based on how binary data is entered (loaded) and retrieved (read):

1. Serial-In Serial-Out (SISO): Data is entered one bit at a time and retrieved one bit at a time. It produces a time delay equal to .
2. Serial-In Parallel-Out (SIPO): Data is entered serially but all bits are available at the output terminals simultaneously.
3. Parallel-In Serial-Out (PISO): Data is loaded into all flip-flops simultaneously and shifted out serially one bit per clock cycle.
4. Parallel-In Parallel-Out (PIPO): Data is loaded simultaneously and retrieved simultaneously. It is essentially a storage register.

Construction:
A 4-bit SISO shift register consists of 4 D-Flip Flops connected in a chain. The clock signal () is applied simultaneously to all flip-flops.

Logic Connections:

• Input: Serial data is applied to the D input of the first flip-flop ().
• Shifting: The output of connects to input of , to , and so on.
• Output: The final serial output is taken from of the last flip-flop.

Operation:
Initially, let all FFs be cleared ($0000$). Let input data be $1011$.

1. 1st Clock: The bit '1' at input enters . Content: $1000$.
2. 2nd Clock: The '1' moves to , next bit '0' enters . Content: $0100$.
3. 3rd Clock: Bits shift right. Next bit '1' enters. Content: $1010$.
4. 4th Clock: Bits shift right. Last bit '1' enters. Content: $1101$.

To retrieve all data serially, 3 more clock pulses are required to shift the data out from the last stage.

Operation of SIPO:
In a SIPO shift register, data is entered serially (one bit per clock pulse) into the first flip-flop, similar to SISO. However, the outputs of all flip-flops () are accessible simultaneously.

Process:

1. Data bits enter the register sequentially synchronized with the clock.
2. Once all bits are shifted in (after clock cycles), the data becomes available at the parallel output lines simultaneously.

Difference from SISO:

• Output Access: In SISO, data is only available at the final stage (). In SIPO, data is available at every stage ( through ).
• Speed: SIPO allows for faster data processing by subsequent circuits because the whole word is available at once after loading, whereas SISO requires serial retrieval.
• Application: SIPO is commonly used for Serial-to-Parallel data conversion in communication systems.

Concept:
A PISO register allows data to be loaded simultaneously into all flip-flops (Parallel Load) and then shifted out one bit at a time (Serial Shift).

Logic Description:
To support both parallel loading and shifting, combinatorial logic (typically AND-OR gates) is used at the D-input of each flip-flop (except the first one).

• A control line Shift/ is used.

Operation Modes:

1. Parallel Loading (Shift/ = 0):

   • The AND gates associated with parallel inputs () are enabled.
   • On the next clock edge, the parallel data is loaded into the flip-flops ().

2. Serial Shifting (Shift/ = 1):

   • The AND gates connecting to are enabled.
   • The circuit behaves like a SISO register.
   • With every clock pulse, data shifts to the right, and bits exit serially from the last flip-flop.

Asynchronous (Ripple) Counter:

• Clock: The external clock is applied only to the first flip-flop (LSB). Subsequent flip-flops are clocked by the output of the preceding flip-flop.
• Speed: Slower operation due to propagation delay accumulation (Ripple effect).
• Design: Simpler design logic; usually does not require complex combinational logic for state transitions.
• Glitches: Prone to decoding errors (glitches) due to unequal delay.

Synchronous Counter:

• Clock: The clock pulse is applied simultaneously to all flip-flops.
• Speed: Faster operation; propagation delay is determined by a single flip-flop plus gate delay.
• Design: More complex; requires excitation tables and combinational logic (K-maps) to determine flip-flop inputs.
• Glitches: Less prone to glitches as state changes occur simultaneously.

Design Logic:

1. Flip-Flops: Use 3 JK Flip-Flops ().
2. Mode: Set all JK inputs to High () to operate in Toggle Mode.
3. Clocking:
   • Apply external clock () to the clock input of (LSB).
   • Connect the output to the clock input of .
   • Connect the output to the clock input of .

Operation:

• Initial State: .
• CLK 1 (Falling Edge): toggles (). Output: $001$.
• CLK 2 (Falling Edge): toggles (). This transition () triggers to toggle (). Output: $010$.
• CLK 3 (Falling Edge): toggles (). doesn't trigger (rising edge). Output: $011$.
• CLK 4 (Falling Edge): toggles (), triggering (), triggering (). Output: $100$.

This continues until count $111$, after which it resets to $000$.

Propagation Delay in Ripple Counters:
In an asynchronous (ripple) counter, the clock input of a specific stage is driven by the output of the previous stage. This means the second flip-flop cannot change state until the first one has settled, the third must wait for the second, and so on.

• The signal "ripples" through the counter chain.
• This accumulation of delays places a limit on the maximum operating frequency of the counter.

Total Delay Calculation:
If the propagation delay of a single flip-flop is , then for an -bit counter:

Maximum Frequency:
To ensure valid data is read, the clock period must be greater than the total delay:

This creates a trade-off: as the number of bits () increases, the maximum speed decreases.

Steps for Synchronous Counter Design:

1. State Diagram: Draw the state diagram showing the sequence of states required (e.g., ). determine the number of flip-flops () needed where number of states.
2. Type of Flip-Flop: Select the type of flip-flop to be used (JK, T, or D).
3. Excitation Table: Write the excitation table for the chosen flip-flop. (e.g., for JK: Determine required inputs for transitions ).
4. State Table: Construct the circuit state table listing:
   • Present State ()
   • Next State ()
   • Required Flip-Flop Inputs (Excitation inputs).
5. Simplification: Use Karnaugh Maps (K-Maps) to simplify the boolean expressions for the flip-flop inputs in terms of the Present State outputs.
6. Logic Diagram: Draw the logic circuit using the simplified boolean expressions and the selected flip-flops.

1. Determine Flip-Flops:
To count from 0 to 7 (), we need 3 T Flip-Flops ().

2. Excitation Table for T Flip-Flop:

• If , then (No Toggle).
• If $Qn
  eq Q{n+1}T=1$ (Toggle).

3. State Table:

4. K-Map Simplification:

• For : The column is all 1s.
• For : is high when .
• For : is high when AND .

5. Logic Diagram:

• connected to Logic 1 ().
• connected to .
• connected to the output of an AND gate with inputs and .
• Clock connected to all FFs simultaneously.

Concept:
A standard 3-bit ripple counter counts from 0 to 7 (). To make a MOD-6 counter (states $0,1,2,3,4,5$), the counter must reset to $0$ immediately when it attempts to enter state 6 ($110$).

Design Steps:

1. Flip-Flops: Use 3 JK Flip-Flops ().
2. Connections: Connect as a standard ripple up-counter (output of to clock of ). Set .
3. Reset Logic (Feedback):
   • Desired End State: Reset when count reaches 6.
   • Binary for 6: .
   • We need to activate the asynchronous CLEAR (CLR) or RESET inputs of all flip-flops when this state occurs.
   • Since CLR is typically active-low (bubble), we use a NAND gate.
   • Inputs to NAND Gate: and . (We don't need since state 6 is the first time and are both 1).

Operation:

• Counter counts normally.
• At the next clock, counter temporarily goes to $110$.
• NAND gate output goes LOW (since inputs $1,1$).
• This LOW signal triggers the CLR inputs.
• Counter immediately resets to $000$ (glitch state $110$ is very brief).

Definition:
A Ring Counter is a circular shift register where the output of the last flip-flop is connected back to the serial input of the first flip-flop. It is a synchronous counter.

Block Diagram Logic:

• 4 D-Flip Flops ( to ) connected in a chain.
• Clock applied simultaneously.
• Feedback: Output connects to Input .
• Initialization: Unlike standard counters, a Ring Counter must be preset with a specific pattern, typically a single '1' (One-hot encoding). Use Preset/Clear lines to initialize to $1000$.

Working (Assuming initial state 1000):

1. Initial: . ($1000$)
2. Clock 1: The '1' shifts to . ($0100$)
3. Clock 2: The '1' shifts to . ($0010$)
4. Clock 3: The '1' shifts to . ($0001$)
5. Clock 4: The '1' from feeds back to . ($1000$)

The single '1' circulates through the ring. Total states = (where is number of bits).

Definition:
A Johnson Counter (or Twisted Ring Counter) is a modification of the Ring Counter where the inverted output of the last flip-flop () is connected to the input of the first flip-flop.

Design Difference:

• Ring Counter: Feedback is .
• Johnson Counter: Feedback is .

Working (4-bit, Initial 0000):

1. Start: $0000$. .
2. CLK 1: '1' enters . State: $1000$.
3. CLK 2: State: $1100$.
4. CLK 3: State: $1110$.
5. CLK 4: State: $1111$. Now .
6. CLK 5: '0' enters . State: $0111$.
7. ... Cycles through .

States Comparison:

• Ring Counter (n-bit) has states.
• Johnson Counter (n-bit) has states.

Waveform Description for 4-bit Johnson Counter:

Since visual drawing is not possible, here is the timing sequence description required to draw the waveform:

• CLK: A continuous train of square pulses.
• Q0: Goes HIGH for 4 clocks, then LOW for 4 clocks.
• Q1: Identical to Q0 but delayed by 1 clock period.
• Q2: Identical to Q1 but delayed by 1 clock period.
• Q3: Identical to Q2 but delayed by 1 clock period.

State Sequence:

The frequency of the output waveforms is .

Definition:
A Bidirectional Shift Register is capable of shifting data either to the right or to the left depending on a mode control input.

Logic Construction:
It uses a 4-bit register with combinational logic at the inputs of each flip-flop. A control line, say (Mode), determines the direction.

Logic at each stage ():
Input is driven by a Multiplexer or an AND-OR combination:

Operation:

1. Right Shift ():
   • The logic enables connection from the previous stage () to current input.
   • Data moves .
2. Left Shift ():
   • The logic enables connection from the next stage () to current input.
   • Data moves .

It allows for versatile data manipulation, such as multiplication (shift left) and division (shift right) by 2.

Definition:
A Universal Shift Register is a versatile register that can perform all standard shift register operations: SISO, SIPO, PISO, PIPO, and bidirectional shifting.

Structure:
It consists of flip-flops and a 4:1 Multiplexer (MUX) at the input of each flip-flop to select the mode of operation.

Control Inputs:
Two selection lines, and , control the MUXs.

Function Table:

Operation:
The multiplexer selects the source of the data for the D-flip-flop based on the user's requirement defined by and .

Lock-out Condition:
In a counter with flip-flops, there are possible states. However, the counter design might typically use fewer states (e.g., a MOD-10 counter uses 10 states, leaving 6 unused states).

If the counter accidentally enters one of these unused states (due to noise or power-up glitches) and the design logic does not provide a path back to a valid state, the counter may get stuck in a loop of unused states. This is called Lock-out.

How to Avoid:

1. Self-Correcting Logic: When designing the counter using K-maps, explicitly define the next state for the unused states to return to a valid state (usually $000$).
2. Avoid 'Don't Cares' blindly: Do not treat unused states strictly as 'Don't Cares' () if reliability is critical. Verify that the values chosen by the K-map simplification lead back to the valid sequence.

Goal: Design a counter with sequence .

1. Flip-Flops: 3 JK Flip-Flops ().

2. Key Observations (or via State Table):

• LSB (): Toggles on every clock. .
• Bit 1 (): Toggles when changes from (which is when ). In synchronous logic for a down counter, should toggle when lower bit (or ).
  • .
• Bit 2 (): Toggles when both and are 0.
  • .

Formal Design (Summary):
Use Excitation Table and K-Maps.

Circuit:
AND gates are used to combine the inverted outputs of previous stages to drive the J, K inputs of the next stage.

Applications of Shift Registers:

1. Data Format Conversion: Converting Serial data to Parallel (SIPO) and vice versa (PISO) for interfacing peripherals.
2. Delay Lines: Creating digital time delays.
3. Arithmetic Operations: Multiplication and Division by 2 via shifting.
4. Sequence Generators: Like Pseudo-Random Number Generators (PRNG).

Applications of Counters:

1. Frequency Dividers: Reducing clock frequency (e.g., in digital watches).
2. Event Counting: Counting external pulses or objects.
3. Time Measurement: Measuring time intervals in stopwatches.
4. Addressing: Generating sequential addresses for memory access.
5. ADC: Used in Ramp-type Analog to Digital Converters.

Comparison:

1. Feedback Mechanism:

   • Ring Counter: Direct feedback. Output of last FF () connects to input of first FF ().
   • Johnson Counter: Inverse feedback. Inverted output of last FF () connects to input of first FF ().

2. Number of States (Modulus):

   • Ring Counter: Mod- (where is number of FFs).
   • Johnson Counter: Mod-.

3. Used vs Unused States (Efficiency):

   • Ring Counter: Very inefficient ( valid states out of ).
   • Johnson Counter: More efficient ( valid states out of ).

4. Decoding Logic:

   • Ring Counter: No decoding logic needed to identify a state (outputs are already one-hot).
   • Johnson Counter: Requires decoding gates (e.g., AND gates) to detect specific states.

Logic Circuit:
A PIPO register is the simplest register configuration.

• It consists of 4 D-Flip Flops.
• There are no interconnections between the outputs of one flip-flop and the inputs of the next.
• Inputs: Parallel data lines are connected directly to the D inputs of the respective flip-flops.
• Clock: The CLK signal is connected to all flip-flops.

Operation:

1. Data Setup: The binary word to be stored is applied to the data inputs.
2. Loading: On the active edge of the clock pulse (e.g., rising edge), the values at inputs are latched into the flip-flops.
3. Output: The stored data is immediately available at the outputs through .

It is mainly used for temporary storage (buffer) of data.