Unit4 - Subjective Questions

Difference between Combinational and Sequential Circuits:

An SR Latch (Set-Reset Latch) is the simplest form of sequential circuit constructed using two cross-coupled NOR gates.

Construction:

• The output of the first NOR gate () is fed back as an input to the second NOR gate.
• The output of the second NOR gate () is fed back as an input to the first NOR gate.

Operation:

1. (No Change): The outputs remain in their previous state. If , it forces , which reinforces .
2. (Reset): The high input forces the output to $0$. Consequently, becomes $1$. This is the Reset state.
3. (Set): The high input forces to $0$, which in turn allows to become $1$. This is the Set state.
4. (Invalid): Both outputs try to go to $0$ (due to NOR property), violating the complementary rule (). This state is forbidden.

Comparison between Latch and Flip-Flop:

1. Triggering Method:

   • Latch: It is Level Triggered. The output changes state as long as the enable input is active (high or low).
   • Flip-Flop: It is Edge Triggered. The output changes state only at specific transitions of the clock signal (rising edge or falling edge).

2. Sensitivity:

   • Latch: Sensitive to glitches or noise on the control signal because it is transparent during the active level.
   • Flip-Flop: Less sensitive to noise on the control signal as it only samples input at the edge.

3. Circuit Complexity:

   • Latch: Basic building block, simpler circuit (fewer gates).
   • Flip-Flop: Usually constructed using two latches (Master-Slave) or complex gating, consuming more power and area.

4. Use Cases:

   • Latch: Used in asynchronous designs, buffer storage.
   • Flip-Flop: Used in synchronous systems, registers, counters.

Clocked SR Flip-Flop:
It consists of a basic NAND latch with two additional NAND gates at the input controlled by a Clock (CLK) signal.

Logic Diagram:
Inputs and are connected to the latch through NAND gates only when .

Working Principle:

1. : The gating NAND gates output '1' regardless of and . The basic latch holds the previous state ().
2. : The circuit responds to inputs and .
   • : Inputs to the latch are $1,1$. No change in state.
   • : The Reset path is activated, making .
   • : The Set path is activated, making .
   • : Inputs to the latch become $0,0$, leading to an invalid state (Race condition/Indeterminate).

Characteristic Equation:
(Valid only when )

JK Flip-Flop:
The JK Flip-Flop is a modification of the SR Flip-Flop designed to handle the invalid state (). Inputs are labeled (Jump/Set) and (Kill/Reset).

Modification:
Feedback is provided from the outputs back to the inputs:

• Output is ANDed with and .
• Output is ANDed with and .

Operation:

1. : No change in state ().
2. : Resets the flip-flop ().
3. : Sets the flip-flop ().
4. (Toggle Mode):
   • In an SR FF, this is invalid.
   • In a JK FF, due to feedback, if , the input becomes active, resetting the FF. If , the input becomes active, setting the FF.
   • The output toggles (complements) its previous state: .

Characteristic Equation:

Race Around Condition:
In a level-triggered JK Flip-Flop, when and :

1. The output is supposed to toggle ().
2. However, if the propagation delay of the flip-flop () is much less than the pulse width of the clock (), the output will toggle, feed back to the input, and toggle again multiple times within a single clock pulse.
3. This causes the output to oscillate between 0 and 1 indeterminately. This is called the Race Around Condition.

Condition for Race Around:

Methods to Avoid:

1. Edge Triggering: Using edge-triggered flip-flops that only sample inputs at the transition.
2. Master-Slave Configuration: Using two flip-flops (Master and Slave) cascaded, where the Master works on one level (or edge) and the Slave on the other, isolating the output from the input during the active clock.
3. Delay: Keeping the clock pulse width very small (), though this is practically difficult.

Master-Slave JK Flip-Flop:
It consists of two latches connected in series: the first is the 'Master' and the second is the 'Slave'.

Construction:

• Master: Driven by the Clock (). Inputs are and .
• Slave: Driven by the inverted Clock (). Inputs are the outputs of the Master.

Working:

1. When (High):
   • The Master is active and accepts inputs and .
   • The Slave is inactive (disabled) because its clock is 0. Ideally, the Master's output settles, but the Slave output () does not change yet.
2. When (Low):
   • The Master becomes inactive and holds its data.
   • The Slave becomes active (since ). It reads the output of the Master and passes it to the final output .

Significance:
Since the output changes only when goes low, the feedback to the inputs and does not change while the Master is active. This eliminates the Race Around Condition found in standard level-triggered JK flip-flops.

D Flip-Flop (Data or Delay Flip-Flop):
It has a single data input . It is constructed from an SR or JK flip-flop by ensuring inputs are complementary ( or ).

Derivation of Characteristic Equation:
Using the Excitation table logic or K-Map for :

• When , Next State is 0.
• When , Next State is 1.
• The next state follows the input regardless of the current state .

Equation:

Significance:

• Storage: It stores 1 bit of data. If , it stores 1; if , it stores 0.
• Delay: The output follows the input after a clock cycle delay, making it useful for shift registers and buffers.
• It eliminates the invalid state of the SR flip-flop.

T Flip-Flop (Toggle Flip-Flop):
It is a single-input version of the JK Flip-Flop where inputs and are tied together. The input is denoted by .

Operation:

1. (): The flip-flop holds its current state (No Change).
2. (): The flip-flop toggles its output ().

Derivation (K-Map):
Looking at the table, is high when inputs are or . This corresponds to the XOR operation.

Characteristic Equation:

Excitation Table:
An excitation table lists the required inputs to specific flip-flops to achieve a desired transition from a present state () to a next state (). It is essential for synthesis (converting one FF to another).

Edge Triggering:
In edge-triggered flip-flops, the circuit only responds to the control inputs when the clock signal transitions from one level to another. It ignores inputs while the clock is stable (high or low).

1. Positive Edge Triggering:

• Definition: The flip-flop samples inputs and changes state only on the Rising Edge of the clock (transition from Logic 0 to Logic 1).
• Symbol: A triangle () at the clock input pin.
• Operation: Events occur at . Between rising edges, inputs can change without affecting .

2. Negative Edge Triggering:

• Definition: The flip-flop samples inputs and changes state only on the Falling Edge of the clock (transition from Logic 1 to Logic 0).
• Symbol: A triangle with a bubble (circle) at the clock input pin.
• Operation: Events occur at .

Waveform Interpretation:
For a D Flip-Flop:

• Pos-Edge: takes value of exactly when CLK goes .
• Neg-Edge: takes value of exactly when CLK goes .

Conversion: SR Flip-Flop to JK Flip-Flop

Goal: Design logic to drive and inputs using external and inputs to mimic JK behavior.

Step 1: Conversion Table
We combine the JK Excitation Table with the SR Excitation requirements.

Step 2: K-Map Simplification

• For S: Group minterms where output is 1. We find
• For R: Group minterms where output is 1. We find

Step 3: Logic Diagram

• Connect an AND gate with inputs and to the pin.
• Connect an AND gate with inputs and to the pin.
• This converts the SR FF into a JK FF.

Conversion: JK to D

Objective: Derive values for and in terms of such that the JK FF acts like a D FF ().

Step 2: Simplification

• For J: From the table, when . When . Thus, .
• For K: From the table, when . When . Thus, .

Step 3: Circuit Implementation

1. Connect input directly to the input.
2. Connect input through a NOT gate (inverter) to the input.
   This effectively creates a D Flip-Flop.

General Procedure for Flip-Flop Conversion:

1. Identify Available and Required: Determine which Flip-Flop is available (Target/Actual hardware) and which Flip-Flop behavior is desired (Source).
2. Draw Conversion Table: Create a table with the following columns:
   • Inputs of the Desired Flip-Flop (e.g., if making a JK, columns J and K).
   • Current State ().
   • Next State () determined by the logic of the Desired Flip-Flop.
   • Excitation Inputs of the Available Flip-Flop (e.g., if using SR, columns S and R) required to transition from to .
3. K-Map Minimization: Derivate Boolean expressions for the inputs of the Available Flip-Flop in terms of the Desired inputs and .
4. Circuit Realization: Draw the combinational logic circuit based on the expressions derived to drive the inputs of the Available Flip-Flop.

Conversion: D to T

Available: D Flip-Flop ()
Required: T Flip-Flop ()

Step 1: Logic
We need to drive the input such that the output toggles when and holds when .
Since for a D FF, , we simply need to equal the characteristic equation of the T FF.

Step 2: Equation

From the table, is high when inputs are or . This confirms .

Implementation:
Connect an XOR gate with inputs and to the input.

Transparency in D-Latch:

1. Definition: A D-Latch is often called a "Transparent Latch" because of how it handles data when the Enable (Clock) signal is active (High).
2. Working:
   • When Enable = 1: The output follows the input essentially immediately (after gate propagation delay). If changes multiple times while Enable is high, will change correspondingly. The latch is "transparent"; data passes right through it.
   • When Enable = 0: The latch becomes opaque. The output retains the last value present at just before the Enable signal went low. Changes in do not affect .
3. Contrast: This is different from an edge-triggered D Flip-Flop, which only samples data at the instant of the clock edge and is opaque at all other times.

Derivation of JK Characteristic Equation:

Step 1: Truth Table / Characteristic Table
We look at the next state based on inputs and current state .

Step 2: K-Map for
Variables: .

• Minterms for 1: .

Step 3: Grouping

• Group 1: Combine and . changes (0 to 1), is 0. is 1. Term:
• Group 2: Combine and . changes, is 1. is 0. Term:

Step 4: Final Equation

Conversion: JK to T

Available: JK Flip-Flop ()
Required: T Flip-Flop ()

Step 2: Logic Derivation

• For J: Compare T and J columns. When T=0, J=0. When T=1, J=1.
• For K: Compare T and K columns. When T=0, K=0. When T=1, K=1.

Conclusion:
Connect both and inputs together and connect them to the input . This converts the JK Flip-Flop into a T Flip-Flop (Toggle Mode).

Preset (PRE) and Clear (CLR) Inputs:

Most practical flip-flop ICs have direct inputs called Preset and Clear. These are Asynchronous Inputs, meaning they affect the output immediately, independent of the Clock signal.

1. Preset (PRE or ):

   • Used to set the Flip-Flop state to Logic 1 () immediately.
   • Usually active low. When , becomes 1 regardless of or .

2. Clear (CLR or ):

   • Used to reset the Flip-Flop state to Logic 0 () immediately.
   • Usually active low. When , becomes 0.

Usage:
These inputs are used for system initialization (Power-on Reset) to ensure the circuit starts from a known state before the clock starts running.

Master-Slave D Flip-Flop:
Constructed using two D-Latches in series with inverted enable signals.

Construction:

1. Master D-Latch: Input , Enable input connected to .
2. Slave D-Latch: Input comes from Master's output (), Enable input connected to (Inverted Clock).

Operation:

1. :
   • Master is enabled (Transparent). follows .
   • Slave is disabled (Opaque). Output holds previous value.
2. :
   • Master is disabled. holds the value of captured just before the falling edge.
   • Slave is enabled. It reads and updates .

Result:
Data is sampled at the falling edge of the clock (effectively edge-triggered behavior), isolating input from output during the clock cycle.