Unit6 - Subjective Questions

Architecture of ROM:

A Read-Only Memory (ROM) is a combinational circuit that stores permanent binary information. Its architecture consists of:

1. k input address lines: These lines determine which word is to be selected.
2. Decoders: The inputs are decoded into distinct minterms.
3. OR Gates: The outputs of the decoder are connected to OR gates via programmable connections (fuses).
4. n output lines: represent the data word size.

Storage Mechanism:

• A ROM is essentially a device that implements a truth table. The inputs provide the address, and the outputs provide the data.
• Ideally, it consists of a decoder and OR gates.
• The intersections between the decoder outputs and the OR gate inputs contain fuses. If a fuse is intact, it represents a logic '1' (or connection); if blown, it represents logic '0'.
• Therefore, a ROM can implement any combinational circuit with inputs and outputs.

Comparison between SRAM and DRAM:

Programmable Logic Array (PLA):

A PLA is a type of Programmable Logic Device (PLD) used to implement combinational logic circuits. Unlike a PROM, where the AND array is fixed, in a PLA, both the AND array and the OR array are programmable.

Internal Structure:

1. Input Buffers/Inverters: Provide both the true and complemented forms of inputs.
2. Programmable AND Array: Forms the product terms. For inputs, we can program specific product terms (P-terms) rather than generating all minterms.
3. Programmable OR Array: Sums the product terms to generate the final output functions.
4. Output Buffers: Often include XOR gates for programmable polarity (active high or active low).

Logic Implementation:

If we have functions and with inputs , the PLA implements equations like:

Advantages: It is more efficient than a PROM when the number of required product terms is far less than the total number of minterms ().

Step 1: Simplify the Boolean Functions using K-Maps.

For :

• Grouping 0, 1, 2, 4 results in terms: (0,1), (0,2), (0,4).
• Simplified:

For :

• Minterm 0 is .
• Minterms 5, 6, 7 simplify to .
• This doesn't share many terms. Let's look for common terms.
• Alternative Simplification:

Step 2: Identify Product Terms.
To optimize, we look for shared terms. If distinct:

Step 3: PLA Table Programming.

(Note: In a real PLA design, we try to maximize shared terms to reduce the number of AND gates used).

The three major types of combinational Programmable Logic Devices (PLDs) differ in the programmability of their AND and OR arrays:

1. PROM (Programmable Read-Only Memory):

   • AND Array: Fixed (Hardwired to generate all minterms).
   • OR Array: Programmable.
   • Use: Ideal for memory storage or lookup tables where all address combinations are defined.

2. PLA (Programmable Logic Array):

   • AND Array: Programmable.
   • OR Array: Programmable.
   • Use: Most flexible combinational logic implementation; can share product terms between outputs. Slower and more expensive than PALs.

3. PAL (Programmable Array Logic):

   • AND Array: Programmable.
   • OR Array: Fixed.
   • Use: Easier to manufacture and faster than PLAs. The output logic for a specific pin is limited to the fixed number of OR inputs available.

Concept of Refreshing in DRAM:

A Dynamic RAM (DRAM) cell stores a binary bit as an electrical charge on a small capacitor.

Why it is required:

1. Leakage: Capacitors are not perfect; the charge stored on them leaks away over time due to substrate leakage currents in the transistor.
2. Data Loss: If the charge leaks below a threshold voltage, the logic '1' might be read as logic '0', causing data loss. Typically, data remains valid for only a few milliseconds.

The Refresh Operation:
To prevent data loss, the memory controller must periodically read the data from the cell, amplify it, and write it back to restore the full charge. This process is called refreshing.

• It is done row by row.
• The CPU cannot access the memory during the refresh cycle, which can slightly impact performance.

PAL Architecture:

Programmable Array Logic (PAL) architecture consists of:

1. Programmable AND Array: Inputs are fed into a programmable AND plane to generate product terms.
2. Fixed OR Array: The outputs of the AND array are connected to fixed OR gates.

For example, a specific output might be hardwired to sum exactly 4 product lines. You can program which product terms appear on those lines, but you cannot change the fact that is the sum of those specific lines.

Difference from PLA:

• Flexibility: PLA is more flexible because both arrays are programmable. PAL is less flexible because the OR array is fixed.
• Sharing Terms: In PLA, a product term generated in the AND array can be shared by multiple OR gates (multiple outputs). In PAL, product terms are dedicated to specific OR gates and cannot be shared.
• Speed/Cost: PALs are generally faster and cheaper to manufacture than PLAs because the fixed OR array reduces complexity and internal delay.

Sequential PLDs:

Combinational PLDs (like simple PALs or PLAs) contain only gates. Sequential PLDs include memory elements (Flip-Flops) along with the programmable logic gates, allowing them to implement sequential logic circuits (state machines, counters, registers).

Key Features:

1. Registered Outputs: The output of the combinatorial logic (AND-OR array) is fed into a Flip-Flop (usually D-type) before reaching the output pin.
2. Feedback: The output of the Flip-Flop is fed back into the programmable AND array. This allows the current state to affect the next state logic.
3. Macrocells: A typical SPLD output structure is called a Macrocell. It typically contains sum-of-product logic, a Flip-Flop, and a multiplexer to bypass the Flip-Flop if purely combinational output is needed.

Example: The GAL (Generic Array Logic) devices (e.g., GAL16V8) are common examples of SPLDs.

Field Programmable Gate Arrays (FPGAs):

An FPGA is a semiconductor device containing programmable logic blocks and interconnect circuits. It can be configured by the customer or designer after manufacturing ("in the field"). It offers much higher logic density than CPLDs.

Three Main Components:

1. Configurable Logic Blocks (CLBs):

   • These are the basic logic units. A CLB typically contains Look-Up Tables (LUTs) to implement logic functions, Flip-Flops for storage, and multiplexers.
   • A LUT functions as a small RAM that stores the truth table of a logic function.

2. Programmable Interconnects (Routing):

   • A matrix of wires and programmable switches that connect different CLBs together and connect CLBs to I/O blocks.
   • Routing determines the speed and timing of the signals.

3. Input/Output Blocks (IOBs):

   • These interface the internal logic of the FPGA with the physical pins of the chip.
   • They support various voltage standards and drive strengths.

6-Transistor SRAM Cell Operation:

An SRAM cell stores one bit of data. The standard cell uses 6 MOSFETs.

Structure:

• Storage: Four transistors () form two cross-coupled inverters. This latch structure holds the state (0 or 1) indefinitely as long as power is applied.
  • If point is high, is low, keeping high through feedback.
• Access: Two transistors () serve as access switches controlled by the Word Line (WL). They connect the internal nodes and to the Bit Lines (BL and ).

Operation:

1. Standby: WL = 0. Access transistors are off. The cross-coupled inverters hold the data.
2. Read:
   • Bit lines are pre-charged to or .
   • WL = 1. Access transistors turn on.
   • The stored value at and pulls one bit line slightly up and the other down.
   • A sense amplifier detects the voltage difference.
3. Write:
   • The value to be written is applied to BL and inverted on .
   • WL = 1.
   • The bit line drivers are stronger than the internal inverters, forcing the latch to flip to the new state.

PROM Size Calculation:

A PROM acts as a lookup table.

• Inputs (): Act as the address lines.
• Outputs (): Act as the data lines (word width).
• Address Space: With inputs, there are possible combinations (minterms).

Total Size:
The size of the PROM required is:
where is the number of words (depth) and is the number of bits per word (width).

Example:
To implement a full adder using a PROM:

• Inputs: A, B, Cin ().
• Outputs: Sum, Carry ().
• Calculation:
  • Number of words = .
  • Word length = $2$ bits.
  • Required PROM Size: bits (or 16 bits total capacity).

ROM is classified based on how data is written and erased:

1. Mask ROM (MROM):

   • Programmed by the manufacturer during the fabrication process using a photo mask.
   • Cannot be changed. Lowest cost for high volume.

2. PROM (Programmable ROM):

   • Manufactured blank. Users program it once using a PROM programmer by "blowing fuses".
   • OTP (One-Time Programmable).

3. EPROM (Erasable Programmable ROM):

   • Can be erased and reprogrammed.
   • Erasure: Exposure to strong Ultraviolet (UV) light through a quartz window on the chip package.
   • Entire chip is erased at once.

4. EEPROM (Electrically Erasable PROM):

   • Erased and reprogrammed electrically.
   • Can erase byte-by-byte (byte addressable).
   • Slower than RAM but retains data without power.

5. Flash Memory:

   • A specific type of EEPROM.
   • Erases data in blocks (Sector erase) rather than byte-by-byte, making it faster for block transfers.
   • High density, used in USB drives and SSDs.

Applications of PLAs:

1. Control Logic: Implementing complex state machines and control units in processors.
2. Data Path Circuits: Custom ALUs or decoders.
3. Code Converters: Converting between BCD, Excess-3, or Gray codes.
4. Lookup Tables: For mathematical functions.

Preference over ROM:
For a function with many inputs (), a ROM requires locations.

• ROM Inefficiency: If , a ROM needs 65,536 words, even if the logic function only has 10 minterms equal to '1'. Most of the ROM would store '0's.
• PLA Efficiency: A PLA does not store all minterms. It only generates the specific product terms required for the function. If the function needs only 20 product terms, the PLA AND-array needs only 20 rows, regardless of how large is. This significantly saves silicon area for sparse functions.

Memory Expansion:
Standard memory chips come in specific sizes (e.g., ). To meet system requirements (e.g., ), chips must be combined.

1. Expanding Word Size (Data Width):

• Goal: Increase bits per word (e.g., from 4-bit data to 8-bit data).
• Method: Connect the Address Lines and Chip Select (CS) lines of multiple chips in parallel.
• Data Lines: The data lines of the chips are kept separate to form the wider bus.
• Example: Two chips create one memory.

2. Expanding Memory Capacity (Address Depth):

• Goal: Increase the number of words (e.g., from 1k locations to 2k locations).
• Method:
  • Connect the Data Lines and lower-order Address Lines in parallel.
  • Use the higher-order address bit(s) to drive a Decoder.
  • The decoder outputs connect to the Chip Select (CS) inputs of the memory chips. This ensures only one chip is active at a time based on the address.

Look-Up Table (LUT) in FPGA:

A LUT is the fundamental building block of logic within an FPGA's Configurable Logic Block (CLB).

1. Concept: Instead of creating logic using gates (AND, OR), the FPGA stores the Truth Table of the function in a small, fast SRAM block.
2. Structure: An -input LUT is essentially a bit memory.
   • The logic inputs serve as the address lines for the memory.
   • The memory content is the output of the logic function.
3. Flexibility: A 4-input LUT can implement any possible Boolean function of 4 variables. To change the logic, you simply change the bits stored in the SRAM.
4. Example: To implement , the LUT is loaded with 0, 0, 0, 1. When inputs A=1, B=1 (Address 3) are applied, the LUT outputs 1.

Design Process:

1. Simplify equations using K-Maps:

2. PAL Structure Requirements:

   • Inputs: 4 (A, B, C, D) which provide both true and complement forms.
   • Outputs: 4 (W, X, Y, Z).

3. Programming the PAL:

   • Section W: Program AND array to generate and . The fixed OR gate sums them.
   • Section X: Program AND array to generate and . The fixed OR gate sums them.
   • Section Y: Program AND array for , , .
   • Section Z: Program AND array for , , , .

   Note: If a specific PAL output has a limit of 3 product terms (e.g., a standard PAL structure), equation Z would require simplification or splitting across two outputs, but assuming a standard generic PAL with 4 inputs to the OR gate, this is directly implementable.

Differences between CPLD and FPGA:

1. Architecture:

   • CPLD: Constructive of multiple SPLDs (Macrocells) connected by a central global interconnect matrix. It is closer to PAL/PLA architecture.
   • FPGA: Array of Logic Blocks (CLBs) surrounded by a routing matrix. Architecture is island-style.

2. Granularity:

   • CPLD: Coarse-grained. Better for complex combinational logic with wide inputs.
   • FPGA: Fine-grained (LUT based). Better for complex sequential logic and registers.

3. Performance:

   • CPLD: Deterministic timing (predictable delay) because routing paths are fixed.
   • FPGA: Non-deterministic timing; delay depends on the routing path taken by the software tools.

4. Configuration:

   • CPLD: Usually Non-volatile (EEPROM/Flash based). Retains configuration when power is off. Instant-on.
   • FPGA: Usually Volatile (SRAM based). Requires an external boot ROM to load configuration on power-up.

Structure of a Macrocell:

A Macrocell is the fundamental output logic block of a Sequential PLD (like a GAL or CPLD). It adds flexibility to the output pins.

Components:

1. OR Gate: Takes inputs from the programmable AND array (sum of products).
2. Flip-Flop (D-Type): Allows the device to store state for sequential logic.
3. Multiplexer (MUX): Selects whether the output pin receives:
   • The Combinational output (directly from the OR gate).
   • The Registered output (from the Flip-Flop).
4. Feedback Path: Sends the signal back into the AND array inputs. This feedback can come from the register (for state machines) or the pin (allowing the pin to be used as an input).
5. Output Enable / Tri-state Buffer: Controls whether the pin drives a signal out or acts as a high-impedance input.

Memory Decoding:
The process of selecting a specific memory cell or word based on the binary address applied to the address lines.

Coincident Decoding (2-Dimensional Decoding):
For large memories, a simple linear decoder (1-of-N) becomes too large and slow. Coincident decoding arranges memory cells in a Matrix (Row Column).

1. Address Splitting: The address lines are split into two groups: Row Address and Column Address.
2. Row Decoder: Decodes the row address to activate a specific "Word Line" (selecting an entire row of cells).
3. Column Decoder: Decodes the column address to select specific "Bit Lines" via multiplexers.
4. Intersection: The specific cell located at the intersection of the active Row and active Column is accessed.

Advantage: drastically reduces the size of the decoders. For a 1K memory ($1024$ cells):

• Linear: One decoder.
• Coincident ( matrix): Two decoders.

Advantages of PLDs over Fixed Logic:

1. Reduced Board Space: One PLD can replace multiple standard TTL/CMOS ICs (ANDs, ORs, MUXs, etc.), reducing the physical size of the PCB.
2. Design Flexibility: Changes to the design can be made by reprogramming the device rather than rewiring the board or replacing chips.
3. Reliability: Fewer packages and interconnections (solder joints) lead to higher system reliability.
4. Security: Designs within PLDs can often be secured with a security bit, preventing competitors from copying the circuit logic.
5. Faster Prototyping: Designers can program and test changes in minutes, reducing development time.