Unit 5: Sequential Logic Circuits Applications

1. Introduction to Registers

In digital electronics, a register is a sequential logic circuit capable of storing multiple bits of data. It is constructed using a group of Flip-Flops (FFs).

• Storage Capacity: An -bit register consists of flip-flops and can store bits of binary information.
• Basic Operation: Registers are driven by a common clock signal to ensure synchronous operation.

2. Shift Registers

A Shift Register is a cascade of flip-flops where the output of one flip-flop is connected to the input of the next. They share a common clock pulse, causing data to shift position with every cycle.

2.1 Basic Modes of Operation

Shift registers are classified based on how data enters and leaves the register.

A. Serial-In Serial-Out (SISO)

• Operation: Data enters the register one bit at a time and leaves one bit at a time.
• Latency: For an -bit register, it takes clock cycles to load data and cycles to shift it out (total delay depends on application).
• Application: Data transmission over a single wire, temporal delay generation.

B. Serial-In Parallel-Out (SIPO)

• Operation: Data is entered serially (one bit per clock) but outputs are taken from all flip-flops simultaneously once the register is loaded.
• Application: Serial-to-Parallel conversion (e.g., receiving data from a communication line to a processor bus).

C. Parallel-In Serial-Out (PISO)

• Operation: Bits are loaded into all flip-flops simultaneously (Parallel Load) and then shifted out one by one.
• Control: Requires a Shift/ control line.
  • When control is LOW (Load): Input gates allow parallel data entry.
  • When control is HIGH (Shift): Inter-flip-flop connections are enabled to shift data.
• Application: Parallel-to-Serial conversion (e.g., sending data from a processor to a USB port).

D. Parallel-In Parallel-Out (PIPO)

• Operation: Data is loaded simultaneously and appears at the output simultaneously. There is no shifting of bits between flip-flops.
• Application: Buffer storage, temporary data holding.

2.2 Bidirectional Shift Register

A bidirectional shift register can shift data either to the right or to the left, depending on a control signal (Mode Control, ).

• Design: Uses logic gates (AND-OR combination) at the input of each flip-flop to select the data source.
• Logic:
  • If (Right): The input to flip-flop comes from flip-flop .
  • If (Left): The input to flip-flop comes from flip-flop .

2.3 Universal Shift Register

A Universal Shift Register is the most versatile register, capable of performing all shift register functions. It typically uses 4x1 Multiplexers at the input of each D Flip-Flop.

Modes of Operation (controlled by select lines ):

3. Shift Register Counters

These are specialized counters created by feeding the output of a shift register back to its input.

3.1 Ring Counter

A Ring Counter is a circular shift register.

• Construction: The output of the last flip-flop () is connected directly to the input of the first flip-flop ().
• Initialization: It must be pre-set with a single '1' (e.g., 1000 for a 4-bit counter).
• Operation: The '1' circulates through the register.
  • Clock 1: 1000
  • Clock 2: 0100
  • Clock 3: 0010
  • Clock 4: 0001
• Modulus: An -bit ring counter has valid states.
• Disadvantage: Not self-starting; if it enters an invalid state (e.g., 0000 or 1100), it stays there or loops incorrectly unless reset logic is added.

3.2 Johnson Ring Counter (Twisted Ring)

• Construction: The inverted output of the last flip-flop () is connected to the input of the first flip-flop ().
• Operation:
  • Start: 0000
  • Clock 1: 1000 (Inverse of last 0 feeds in as 1)
  • Clock 2: 1100
  • Clock 3: 1110
  • Clock 4: 1111
  • Clock 5: 0111 (Inverse of last 1 feeds in as 0)
  • ...and so on.
• Modulus: An -bit Johnson counter has valid states.
• Advantage: Uses half the flip-flops of a Ring counter for the same number of states; decodable states.

4. Introduction to Counters

A counter is a sequential circuit that cycles through a prescribed sequence of states upon the application of input pulses.

Classification

1. Asynchronous (Ripple) Counters: The clock is applied only to the first flip-flop. Subsequent flip-flops are clocked by the output of the previous one.
2. Synchronous Counters: The clock is applied to all flip-flops simultaneously.

5. Design of Asynchronous (Ripple) Counters

Characteristics

• Simplicity: Minimal hardware (gates) required.
• Speed: Slower due to propagation delay accumulation (Ripple effect).
• Flip-Flop Used: Usually JK Flip-Flops (inputs tied high) or T Flip-Flops in toggle mode.

Design Steps for MOD-N Asynchronous Counter

1. Determine Flip-Flops: Find such that .
2. Clocking Logic:
   • Up Counter: Connect of FF(i) to Clock of FF(i+1) (assuming negative edge trigger).
   • Down Counter: Connect of FF(i) to Clock of FF(i+1) (assuming negative edge trigger).
3. Truncated Sequence (MOD < ):
   • If the counter is MOD-10 (BCD), it counts 0-9. At count 10 (binary 1010), it must reset.
   • Feedback Logic: Use a NAND gate. Connect the High outputs of the specific state to the NAND inputs. Connect the NAND output to the asynchronous CLEAR (CLR) input of all flip-flops.
   • Example (MOD-10): At 1010 (), and . Connect and to NAND inputs. NAND output to CLR.

6. Design of Synchronous Counters

Characteristics

• Speed: Faster; no cumulative delay because all FFs trigger at once.
• Complexity: Requires more combinational logic (gates) to determine the next state.

Comprehensive Design Procedure

To design a Synchronous Counter (e.g., MOD-6 or Random Sequence):

Step 1: State Diagram and Table

Define the sequence.

• Example: (MOD-4).

Step 2: Determine Number of Flip-Flops

Calculate where Number of States.

Step 3: Select Flip-Flop Type

JK Flip-Flops are most common due to their versatility.

Step 4: Excitation Table

You must know the excitation table of the chosen FF to determine inputs based on the Present State () and Next State ().

(Note: X = Don't Care)

Step 5: Construct the Circuit Excitation Table

Create a table listing:

1. Present State bits.
2. Next State bits.
3. Required Inputs for each Flip-Flop (e.g., ) derived using the table above.

Step 6: K-Map Simplification

1. Create a Karnaugh Map for every input (, etc.) using the Present State bits as the variables.
2. Simplify the boolean expressions.

Step 7: Logic Diagram

Draw the flip-flops connected to the common clock. Use logic gates to implement the simplified boolean expressions for the J and K inputs.

Comparison: Asynchronous vs. Synchronous