Unit 4 - Notes

ECE213 6 min read

Unit 4: Introduction to Sequential Logic Circuits

1. Overview of Sequential Logic

Unlike combinational logic circuits, where the output depends solely on the current inputs, sequential logic circuits depend on both the current inputs and the past history of inputs (current state).

Key Characteristics

Memory: They possess a memory element to store the previous state.
Feedback: The output is fed back to the input.
Clock: Most sequential circuits are controlled by a timing signal called a clock.

Comparison: Combinational vs. Sequential

Feature	Combinational Logic	Sequential Logic
Output	Depends only on current inputs.	Depends on current inputs and current state (past outputs).
Memory	No memory elements.	Contains memory elements (Flip-Flops/Latches).
Feedback	No feedback path.	Feedback path exists.
Clock	Not required.	Usually required (for synchronous circuits).
Examples	Adders, Encoders, Mux.	Counters, Registers, Flip-Flops.

2. Latches vs. Flip-Flops

Both are bistable elements (two stable states: 0 and 1), but they differ in how they change state.

Latch: Asynchronous, Level-Triggered. The output changes as soon as the input changes, provided the enable signal is active (high or low level).
Flip-Flop: Synchronous, Edge-Triggered. The output changes only at specific transitions of the clock signal (rising or falling edge).

3. Basic Sequential Circuits (Latches)

3.1 The SR Latch (Set-Reset)

The most basic storage element. It can be constructed using NOR gates or NAND gates.

SR Latch using NOR Gates (Active High)

S (Set): Sets output $Q$ to 1.
R (Reset): Resets output $Q$ to 0.
Logic: $Q$ and $\bar{Q}$ are outputs.

S	R	$Q_{next}$	State
0	0	$Q_n$	No Change (Memory)
0	1	0	Reset
1	0	1	Set
1	1	Invalid	Forbidden (Both outputs go to 0)

SR Latch using NAND Gates (Active Low)

Inputs are often denoted as $\bar{S}$ and $\bar{R}$ . Ideally kept at logic 1.

Logic 0 on $\bar{S}$ sets the latch.
Logic 0 on $\bar{R}$ resets the latch.
$\bar{S}=0, \bar{R}=0$ is the forbidden state.

3.2 The Gated SR Latch

Adds an Enable (E) or Clock (CLK) input to the basic SR latch. The inputs S and R allow state changes only when $E = 1$ .

3.3 The D Latch (Data/Transparent Latch)

Designed to prevent the "Forbidden" state of the SR latch. It ensures $S$ and $R$ are never equal to 1 at the same time.

Construction: Connect input $D$ directly to $S$ , and connect $D$ through an inverter (NOT gate) to $R$ .
Behavior: When Enable = 1, $Q$ follows $D$ (Transparent). When Enable = 0, $Q$ holds the last value.

En	D	$Q_{next}$
0	X	$Q_n$ (No Change)
1	0	0 (Reset)
1	1	1 (Set)

4. Triggering Methods

Level Triggering

High Level: Circuit responds when Clock is Logic 1.
Low Level: Circuit responds when Clock is Logic 0.
Disadvantage: If the input changes multiple times while the clock is active, the output will change multiple times within one clock cycle (glitching).

Edge Triggering

Positive Edge (Rising): Circuit responds only on the transition from 0 to 1 ( $\uparrow$ ).
Negative Edge (Falling): Circuit responds only on the transition from 1 to 0 ( $\downarrow$ ).
Advantage: Essential for synchronous systems; allows precise timing control.

5. Flip-Flops

5.1 SR Flip-Flop

An edge-triggered version of the Gated SR Latch.

Symbol: Block with S, R, CLK inputs and $Q, \bar{Q}$ outputs.
Characteristic Equation: $Q_{n+1} = S + \bar{R}Q_n$ (Valid only if $SR=0$ )

CLK	S	R	$Q_{n+1}$	State
$\uparrow$	0	0	$Q_n$	Hold
$\uparrow$	0	1	0	Reset
$\uparrow$	1	0	1	Set
$\uparrow$	1	1	?	Invalid

5.2 D Flip-Flop (Delay)

The most common flip-flop used in digital systems (registers, counters). It captures the value of input D at the clock edge.

Characteristic Equation: $Q_{n+1} = D$

CLK	D	$Q_{n+1}$	Description
$\uparrow$	0	0	Reset
$\uparrow$	1	1	Set

5.3 JK Flip-Flop

Designed to solve the "Forbidden State" ( $S=R=1$ ) of the SR Flip-Flop.

J acts like Set.
K acts like Reset.
Feedback: Output $Q$ is fed back to $K$ , and $\bar{Q}$ is fed back to $J$ .
Characteristic Equation:

$Q_{n+1} = J\bar{Q}_n + \bar{K}Q_n$

Truth Table:

CLK	J	K	$Q_{n+1}$	State
$\uparrow$	0	0	$Q_n$	No Change
$\uparrow$	0	1	0	Reset
$\uparrow$	1	0	1	Set
$\uparrow$	1	1	$\bar{Q}_n$	Toggle

Race Around Condition

In a level-triggered JK flip-flop (or if the clock pulse width is too wide), if $J=K=1$ , the output toggles continuously ( $0 \to 1 \to 0 \to 1$ ) within a single clock pulse. This leads to an indeterminate state.

Solution: Use Edge Triggering or a Master-Slave configuration.

5.4 T Flip-Flop (Toggle)

A modification of the JK Flip-Flop where inputs J and K are connected together ( $J=K=T$ ). Used extensively in counters.

Characteristic Equation: $Q_{n+1} = T \oplus Q_n$ (T XOR Q)

CLK	T	$Q_{n+1}$	State
$\uparrow$	0	$Q_n$	No Change
$\uparrow$	1	$\bar{Q}_n$	Toggle

6. Master-Slave Flip-Flop

The Master-Slave (M-S) JK Flip-Flop is a cascade of two latches designed to eliminate the Race Around Condition.

Structure

Master: A gated latch controlled by $CLK$ .
Slave: A gated latch controlled by inverted clock ( $\overline{CLK}$ ).

Operation

CLK = 1 (High):
- The Master is active and accepts inputs J and K.
- The Slave is inactive (isolated).
CLK = 0 (Low):
- The Master becomes inactive (holds data).
- The Slave becomes active and reads the output of the Master.

Result: The output $Q$ changes only once per clock cycle (at the falling edge), making it a true edge-triggered device logically, preventing uncontrolled toggling.

7. Conversion of Basic Flip-Flops

To convert a given Flip-Flop (Available) into a target Flip-Flop (Required), combinational logic is added to the inputs.

General Design Procedure

Identify the Target FF (what you want) and the Available FF (what you have).
Draw the Characteristic Table of the Target FF.
Add a column for the Excitation Table of the Available FF.
Determine the logic expressions for the Available FF inputs using K-Maps.
Draw the circuit.

Excitation Tables (Reference for Conversion)

These tables tell you: "If I am at state $Q_n$ and want to go to $Q_{n+1}$ , what inputs do I need?"

$Q_n$	$Q_{n+1}$	S R	J K	D	T
0	0	0 X	0 X	0	0
0	1	1 0	1 X	1	1
1	0	0 1	X 1	0	1
1	1	X 0	X 0	1	0

(Note: X = Don't Care)

Example: SR to JK Flip-Flop

Target: JK (Inputs J, K)
Available: SR (Inputs S, R)

Table Setup:

J	K	$Q_n$	$Q_{n+1}$ (Target)	Required S	Required R
0	0	0	0	0	X
0	0	1	1	X	0
0	1	0	0	0	X
0	1	1	0	0	1
1	0	0	1	1	0
1	0	1	1	X	0
1	1	0	1	1	0
1	1	1	0	0	1

K-Map for S:
- Inputs: J, K, Q. Highs at (1,0,0) and (1,1,0).
- Equation: $S = J\bar{Q}_n$
K-Map for R:
- Inputs: J, K, Q. Highs at (0,1,1) and (1,1,1).
- Equation: $R = KQ_n$
Circuit: Connect External $J$ ANDed with $\bar{Q}$ to the $S$ input. Connect External $K$ ANDed with $Q$ to the $R$ input.

Unit 3

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