Unit 6: Memory and Programmable Logic

1. Introduction to Memory and Logic

Digital systems require storage for data and instructions (Memory) and mechanisms to implement complex Boolean functions (Logic). While logic gates (AND, OR, NOT) are the building blocks, Programmable Logic Devices (PLDs) and Memory Units allow for higher density, flexibility, and reconfigurability in circuit design.

2. Read-Only Memory (ROM)

2.1 Definition and Characteristics

ROM is a type of non-volatile memory that stores information permanently or semi-permanently. Once data is stored, it can be read at any time but cannot be easily or quickly altered during normal system operation.

• Non-Volatile: Retains data even when power is switched off.
• Architecture: Internally, a ROM acts as a combinational circuit with input address lines and output data lines.
  • Decoder (AND Plane): Decodes the inputs into minterms. This part is "Fixed."
  • OR Array (OR Plane): Selectively combines the minterms to produce outputs. This part is "Programmable" (in the sense of defining the connection).

2.2 Types of ROM

1. Mask ROM (MROM):
   • Programmed by the manufacturer during the semiconductor fabrication process using a photo-mask.
   • Cost: High setup cost, very low per-unit cost for mass production.
   • Alterability: Impossible to change once made.
2. PROM (Programmable ROM):
   • Manufactured with all fuses intact (logic 1). Users program it by "blowing" fuses (creating logic 0) using a high-voltage pulse.
   • Alterability: One-time programmable (OTP).
3. EPROM (Erasable Programmable ROM):
   • Can be erased and reprogrammed.
   • Mechanism: Uses floating-gate transistors. Erasing is done by exposing the chip (via a quartz window) to strong Ultraviolet (UV) light for 20–30 minutes.
4. EEPROM (Electrically Erasable Programmable ROM):
   • Can be erased and reprogrammed electrically without removing the chip from the circuit.
   • Granularity: Can erase byte-by-byte (slower than EPROM for total erasure but more flexible).
5. Flash Memory:
   • A specific type of EEPROM designed for high speed and high density.
   • Difference: Erases data in blocks (sectors) rather than bytes, making it faster for bulk data.

2.3 Applications of ROM

• Firmware storage: BIOS/UEFI in computers.
• Code converters: BCD to 7-Segment lookup tables.
• Function generators: Storing trigonometric tables (Sine/Cosine values).
• Bootstrapping: Storing the initial program loader.

3. Read/Write Memory (RAM)

Random Access Memory (RAM) is volatile memory where data can be written to and read from at comparable speeds. It loses data when power is removed.

3.1 Static RAM (SRAM)

SRAM stores data using bistable latching circuitry (flip-flops).

• Structure: A typical SRAM cell uses 6 Transistors (6T). Four transistors form two cross-coupled inverters (to store the bit), and two serve as access transistors.
• Operation: As long as power is supplied, the feedback loop in the cross-coupled inverters maintains the state (0 or 1).
• Characteristics:
  • Speed: Very fast (access time in nanoseconds).
  • Refresh: No refreshing required.
  • Density: Low (requires 6 transistors per bit).
  • Cost: High per bit.
• Applications: Cache memory (L1, L2, L3) in CPUs.

3.2 Dynamic RAM (DRAM)

DRAM stores data as an electrical charge on a capacitor.

• Structure: Uses 1 Transistor and 1 Capacitor (1T1C). The transistor acts as a switch to let charge in or out of the capacitor.
• Operation:
  • Logic '1': Capacitor is charged.
  • Logic '0': Capacitor is discharged.
• Refreshing: Capacitors leak charge over time. Therefore, the data must be read and rewritten (refreshed) periodically (every few milliseconds) to prevent data loss.
• Characteristics:
  • Speed: Slower than SRAM (due to capacitor charging/discharging and refresh cycles).
  • Density: Very high (small physical footprint per bit).
  • Cost: Low per bit.
• Applications: Main system memory (DDR3, DDR4, DDR5) in computers.

3.3 Comparison: SRAM vs. DRAM

4. Programmable Logic Devices (PLDs) Overview

A PLD is an integrated circuit with a general structure that can be configured by the user to implement specific logic functions. The general architecture consists of an AND plane followed by an OR plane.

• Fixed: Connections are hardwired during manufacturing.
• Programmable: Connections can be made or broken by the user (using fuses, antifuses, or transistors).

5. Programmable Logic Arrays (PLA)

5.1 Architecture

A PLA consists of two programmable planes:

1. Programmable AND Plane: Inputs and their complements are connected to AND gates to generate product terms (P-terms).
2. Programmable OR Plane: The outputs of the AND gates are connected to OR gates to generate the final Sum-of-Products (SOP) output.

5.2 Implementation of Logic

Because both planes are programmable, PLAs are highly flexible.

• Unlike ROM (which generates all minterms), PLA generates only the specific product terms required for the function.
• This allows a PLA to implement functions with a large number of inputs but widely disparate minterms efficiently.

5.3 Pros and Cons

• Pros: Most flexible architecture; efficient for complex logic minimization; can share product terms between different outputs.
• Cons: Slower propagation delay (due to two programmable levels); more expensive and difficult to manufacture than PALs.

5.4 Applications

• Implementing complex combinational logic where term sharing is beneficial.
• Control logic in processors (Datapath control).

6. Programmable Array Logic (PAL)

6.1 Architecture

PAL was developed to overcome the speed and cost disadvantages of PLAs.

1. Programmable AND Plane: Selectable product terms.
2. Fixed OR Plane: The connections between the AND gates and the OR gates are hardwired.

6.2 Implementation of Logic

Since the OR array is fixed, each output function is limited to a specific number of product terms (e.g., an output might be restricted to summing a maximum of 8 product terms).

6.3 Pros and Cons

• Pros: Faster than PLA (only one programmable level); cheaper to manufacture; easier to program.
• Cons: Less flexible than PLA; cannot share product terms between outputs (if a P-term is needed for two outputs, it must be generated twice).

6.4 Applications

• Address decoding.
• Simple state machines.
• Multiplexing and de-multiplexing.

7. Sequential PLDs

Combinational PLDs (PAL/PLA) consist only of logic gates. Sequential PLDs add memory elements (Flip-Flops) to the structure to create state machines and sequential circuits.

7.1 Architecture (SPLD - Simple PLD)

Standard PALs were enhanced by adding a Macrocell at the output stage.

• Macrocell: Typically contains a D Flip-Flop, a Multiplexer (MUX), and feedback paths.
• Functionality:
  • The MUX selects whether the output comes directly from the combinational logic (bypassing the Flip-Flop) or from the registered Q output of the Flip-Flop.
  • Feedback: The output is fed back into the programmable AND array, allowing the device to determine the "next state" based on the "current state."

7.2 Generic Array Logic (GAL)

A popular improvement on the PAL.

• Uses EEPROM technology (reprogrammable) instead of bipolar fuses (one-time programmable).
• Features a programmable output macrocell (OLMC - Output Logic Macrocell) that can emulate various PAL architectures.

7.3 Applications

• Finite State Machines (FSM) implementation.
• Counters and Shift Registers.
• Bus interface controllers.
• Sequence generators.

8. Introduction to Field Programmable Gate Arrays (FPGAs)

FPGAs represent a leap from SPLDs (PAL/PLA) and CPLDs (Complex PLDs) in terms of density and architecture. They do not rely on the simple AND-OR plane structure.

8.1 Architecture

FPGAs consist of an "ocean" of programmable logic blocks surrounded by I/O blocks, connected via a programmable routing fabric.

1. Configurable Logic Blocks (CLBs) / Logic Elements (LEs): The heart of the FPGA.
   • LUT (Look-Up Table): Instead of gates, FPGAs use small SRAM blocks (LUTs) to store the truth table of a function. A 4-input LUT can implement any 4-input Boolean function.
   • Flip-Flops: Each CLB contains flip-flops for sequential logic.
2. Programmable Interconnects: A matrix of routing channels and switch boxes that connect CLBs to create complex systems.
3. I/O Blocks (IOBs): Configurable pins that interface with the external circuit (voltage levels, drive strength, tri-state control).

8.2 Comparison: FPGA vs. ASIC vs. Microcontroller

• vs. Microcontroller: FPGAs execute logic in parallel (hardware), whereas microcontrollers execute instructions sequentially (software). FPGAs are much faster for data processing.
• vs. ASIC (Application Specific Integrated Circuit): ASICs are custom chips. FPGAs are "field programmable." ASICs have lower unit cost at high volume and higher performance, but FPGAs allow design updates after deployment and have zero non-recurring engineering (NRE) costs for the chip fabrication.

8.3 Applications

• Prototyping: Validating ASIC designs before expensive manufacturing.
• Digital Signal Processing (DSP): Radar, image processing, software-defined radio.
• Acceleration: Hardware acceleration in data centers (e.g., Bing search, encryption).
• Automotive: Advanced Driver Assistance Systems (ADAS).