1Which of the following implies that the output of a digital circuit depends not only on the present inputs but also on the past history of inputs?
A.Combinational Logic
B.Sequential Logic
C.Boolean Algebra
D.K-Map Logic
Correct Answer: Sequential Logic
Explanation:Sequential logic circuits have memory elements that store the past history of inputs (state), making the output dependent on both current inputs and the previous state.
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2The basic building block of a sequential circuit is:
A.Multiplexer
B.Flip-Flop
C.Decoder
D.Full Adder
Correct Answer: Flip-Flop
Explanation:A flip-flop (or latch) is the fundamental memory element used in sequential circuits to store 1 bit of information.
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3In an SR latch built using NOR gates, which input condition leads to the 'Forbidden' or 'Invalid' state?
A.
B.
C.
D.
Correct Answer:
Explanation:In a NOR-based SR latch, if both and are 1, both outputs and are forced to 0, which violates the complementary rule of flip-flop outputs. This is the forbidden state.
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4What is the characteristic equation for an SR flip-flop?
A.
B.
C.
D.
Correct Answer:
Explanation:The next state becomes 1 if Set () is 1, or if the current state is 1 and Reset () is not active (0). Hence, (with constraint ).
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5A D latch is often referred to as a 'Transparent Latch' because:
A.The output changes immediately when the input changes, provided the Enable is active.
B.It has no propagation delay.
C.The output is always the inverse of the input.
D.It cannot store data.
Correct Answer: The output changes immediately when the input changes, provided the Enable is active.
Explanation:When the enable input is active (high), the output follows the input directly, making the device appear 'transparent'.
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6What is the characteristic equation of a D flip-flop?
A.
B.
C.
D.
Correct Answer:
Explanation:In a D flip-flop, the next state simply takes the value of the input at the active clock edge.
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7The 'Race-around condition' occurs in which type of flip-flop?
A.D Flip-Flop
B.T Flip-Flop
C.SR Flip-Flop
D.JK Flip-Flop
Correct Answer: JK Flip-Flop
Explanation:The race-around condition occurs in a level-triggered JK flip-flop when and . Because the feedback propagation delay is less than the clock pulse width, the output toggles multiple times within a single clock pulse.
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8Which circuit configuration effectively eliminates the Race-around condition?
A.Active Low SR Latch
B.Master-Slave JK Flip-Flop
C.Basic D Latch
D.NAND-based SR Latch
Correct Answer: Master-Slave JK Flip-Flop
Explanation:A Master-Slave configuration separates the input sampling and output changing events using two latches controlled by complementary clocks, preventing the race-around condition.
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9In a JK flip-flop, if and , the output will be:
A.0
B.1
C. (No Change)
D. (Toggle)
Correct Answer: (Toggle)
Explanation:When both inputs and are high, the JK flip-flop complements (toggles) the current state.
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10The characteristic equation of a JK flip-flop is:
A.
B.
C.
D.
Correct Answer:
Explanation:Based on the truth table: If , output tends to 1 (term handles toggle from 0 to 1). If , output stays 1 (term handles holding 1).
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11What is the function of a T flip-flop when ?
A.Set the output to 1
B.Reset the output to 0
C.Toggle the output state
D.Hold the previous state
Correct Answer: Toggle the output state
Explanation:A T (Toggle) flip-flop inverts the stored bit when the input is High (1). It holds the state when is Low (0).
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12The characteristic equation of a T flip-flop is:
A.
B.
C.
D.
Correct Answer:
Explanation:The next state is the Exclusive-OR (XOR) of the input and the current state . If , . If , .
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13Which inputs are required on a JK flip-flop to transition from state to ?
A.
B.
C.
D.
Correct Answer:
Explanation:Using the JK excitation table: To go from 0 to 1, we can Set () or Toggle (). In both cases, must be 1, and corresponds to Don't Care (). Output is .
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14To convert a JK flip-flop into a D flip-flop, how should the inputs be connected?
A.
B.
C.
D.
Correct Answer:
Explanation:A D flip-flop sets Q to 1 when D=1 (requires ) and Q to 0 when D=0 (requires ). This is achieved by connecting to and to .
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15What is the minimum time the input signal must be maintained stable after the clock transition?
A.Setup Time ()
B.Hold Time ()
C.Propagation Delay ()
D.Clock Width ()
Correct Answer: Hold Time ()
Explanation:Hold time is the minimum amount of time the data input must be held stable after the active clock edge to ensure the data is reliably latched.
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16Which symbol generally indicates negative edge triggering on a flip-flop block diagram?
A.A triangle on the clock input
B.A triangle with a bubble on the clock input
C.Just a straight line input
D.A triangle with a square
Correct Answer: A triangle with a bubble on the clock input
Explanation:The triangle (dynamic indicator) represents edge triggering. The bubble (inversion circle) indicates it is active on the negative (falling) edge.
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17To convert an SR flip-flop to a JK flip-flop, the required external logic connections are:
A.
B.
C.
D.
Correct Answer:
Explanation:To mimic JK behavior using SR: When , we need (Set). When , we need (Reset). The logic derived from the excitation table is and .
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18In a Master-Slave flip-flop, when the Clock is High ():
A.The Master is active and the Slave is inactive.
B.The Slave is active and the Master is inactive.
C.Both Master and Slave are active.
D.Both Master and Slave are inactive.
Correct Answer: The Master is active and the Slave is inactive.
Explanation:In a standard Master-Slave arrangement, the Master is gated by CLK and the Slave by . When CLK=1, the Master receives input, but the Slave is isolated.
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19What represents the 'excitation table' of a flip-flop?
A.Inputs vs Next State
B.Present State and Inputs vs Next State
C.Present State and Next State vs Required Inputs
D.Inputs vs Outputs
Correct Answer: Present State and Next State vs Required Inputs
Explanation:An excitation table lists the Present State () and the Next State () and shows the required inputs (Excitation) to achieve that transition.
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20How is a T flip-flop constructed using a JK flip-flop?
A.Connect to $1$ and to $0$
B.Connect to $0$ and to $1$
C.Connect both and to the input
D.Connect to and to
Correct Answer: Connect both and to the input
Explanation:If and are tied together to input : When , (No Change). When , (Toggle). This matches T flip-flop behavior.
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21For a D flip-flop, determine the required input to transition from to .
A.0
B.1
C.Don't Care ()
D.Depends on Clock
Correct Answer: 0
Explanation:For a D flip-flop, . To get a next state of 0, the input must be 0.
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22Inputs usually labeled 'PRESET' and 'CLEAR' on a flip-flop are generally:
A.Synchronous inputs
B.Asynchronous inputs
C.Clock inputs
D.Power inputs
Correct Answer: Asynchronous inputs
Explanation:PRESET and CLEAR are typically asynchronous, meaning they override the clock and other inputs to immediately set or reset the flip-flop state.
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23In a NAND-gate based SR latch (active low inputs), the 'Hold' state is achieved when inputs are:
A.
B.
C.
D.
Correct Answer:
Explanation:For an active-low NAND latch, 0 is the active level. If both inputs are 1 (inactive), the latch retains its previous state (Memory/Hold).
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24If the present state of a T flip-flop is 1 and the input T is 1, the next state will be:
A.0
B.1
C.High Impedance
D.Indeterminate
Correct Answer: 0
Explanation:Since , the flip-flop toggles. The inverse of the present state (1) is 0.
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25What is the primary difference between a Latch and a Flip-Flop?
A.Latches are edge-triggered; Flip-flops are level-triggered.
B.Latches are level-triggered; Flip-flops are edge-triggered.
C.Latches have a clock; Flip-flops do not.
D.Latches are slower than Flip-flops.
Correct Answer: Latches are level-triggered; Flip-flops are edge-triggered.
Explanation:Latches respond to the input levels while the enable signal is active. Flip-flops sample the inputs only at specific edges (rising or falling) of the clock.
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26In the excitation table of an SR flip-flop, the transition from requires:
A.
B.
C.
D.
Correct Answer:
Explanation:To go from 0 to 1, the flip-flop must be Set. This requires and .
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27What logic gate is essentially formed by the conversion of a T flip-flop to a D flip-flop?
A.AND gate
B.OR gate
C.XOR gate logic on the input
D.NOT gate
Correct Answer: XOR gate logic on the input
Explanation:To convert D to T, . To convert T to D, we need input to toggle only when . The equation is .
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28Which flip-flop is known as a 'Delay' flip-flop?
A.SR Flip-Flop
B.JK Flip-Flop
C.T Flip-Flop
D.D Flip-Flop
Correct Answer: D Flip-Flop
Explanation:The D flip-flop takes the data input and transfers it to the output at the clock edge, effectively delaying the data by one clock cycle.
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29The Setup Time () is defined as:
A.Time after clock edge data must stay stable.
B.Time required for output to change.
C.Time before clock edge data must be stable.
D.Time required to clear the flip-flop.
Correct Answer: Time before clock edge data must be stable.
Explanation:Setup time is the minimum interval before the active clock edge during which the data input must be held steady for the correct value to be captured.
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30If a JK flip-flop is used as a toggle switch () with a clock frequency of , what is the frequency of the output ?
A.
B.
C.
D.
Correct Answer:
Explanation:In toggle mode, the output changes state once per clock cycle. A full cycle of the output (0 to 1 back to 0) requires two clock cycles. Thus, the frequency is halved.
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31The 'Invalid' state of an SR latch () is avoided in a JK flip-flop by:
A.Forcing the output to 0.
B.Forcing the output to 1.
C.Toggling the current state.
D.Disconnecting the power.
Correct Answer: Toggling the current state.
Explanation:The internal logic of the JK flip-flop uses feedback from and to inputs and respectively, ensuring that $1,1$ results in a toggle rather than an invalid state.
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32Which of the following equations represents the conversion from D flip-flop to T flip-flop (Input driven by external and current state)?
A.
B.
C.
D.
Correct Answer:
Explanation:To make a D FF behave like a T FF: If , must equal (Hold). If , must equal (Toggle). This logic describes XOR: .
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33Which component is added to a basic latch to make it synchronous?
A.Inverter
B.Clock signal gated with inputs
C.Feedback loop
D.Pull-up resistor
Correct Answer: Clock signal gated with inputs
Explanation:A synchronous circuit operates in coordination with a clock signal. Gating the inputs with a clock turns a latch into a gated latch or flip-flop.
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34In the context of Flip-Flop conversion, the 'Target' flip-flop is:
A.The flip-flop we want to build.
B.The flip-flop physically available to use.
C.The external combinational logic.
D.The clock source.
Correct Answer: The flip-flop physically available to use.
Explanation:In conversion problems, the 'Target' or 'Available' flip-flop is the one you physically have, and you add logic to make it behave like the 'Required' or 'Desired' flip-flop.
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35For a JK flip-flop, the excitation requirement for the transition is:
A.
B.
C.
D.
Correct Answer:
Explanation:Transition (Reset or Toggle). Reset requires . Toggle requires . In both cases, must be 1, while can be 0 or 1 ().
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36The Master-Slave flip-flop is constructed using:
A.Two latches connected in parallel.
B.Two latches connected in series with complementary clocks.
C.Two flip-flops connected in series with the same clock.
D.One latch and one buffer.
Correct Answer: Two latches connected in series with complementary clocks.
Explanation:The Master is driven by and the Slave by (or vice versa), arranged in a cascade (series) structure.
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37A bistable multivibrator is another name for:
A.A Clock generator
B.A Flip-Flop
C.An Encoder
D.A Comparator
Correct Answer: A Flip-Flop
Explanation:Bistable means it has two stable states (0 and 1), which defines a flip-flop.
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38In a positive edge-triggered D flip-flop, the output updates when:
A.The clock is High (logic 1).
B.The clock is Low (logic 0).
C.The clock transitions from 0 to 1.
D.The clock transitions from 1 to 0.
Correct Answer: The clock transitions from 0 to 1.
Explanation:Positive edge-triggered means the device responds to the rising edge of the clock pulse.
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39The propagation delay () of a flip-flop is:
A.The time it takes for the clock to rise.
B.The time interval between the triggering edge of the clock and the stabilization of the output change.
C.The time the input must be stable before the clock.
D.The frequency of the clock.
Correct Answer: The time interval between the triggering edge of the clock and the stabilization of the output change.
Explanation:Propagation delay measures the reaction speed of the circuit—how long after the clock edge the new valid output appears.
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40Which logical error allows the Master-Slave JK flip-flop to function correctly where a basic JK flip-flop fails?
A.It fixes fan-out issues.
B.It prevents the output from feeding back to the input while the input is still active (Race-around).
C.It increases the voltage levels.
D.It reduces power consumption.
Correct Answer: It prevents the output from feeding back to the input while the input is still active (Race-around).
Explanation:By isolating the slave (output stage) while the master (input stage) samples data, the feedback path does not see the changing output during the same clock phase.
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41If a T flip-flop has inputs and current state , the next state is:
A.0
B.1
C.Toggle
D.X
Correct Answer: 0
Explanation: implies 'No Change'. Since , remains 0.
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42The excitation table for a T flip-flop shows that to go from to , must be:
A.0
B.1
C.X
D.Clocked
Correct Answer: 1
Explanation:The state is changing (), which requires a Toggle operation. Therefore, .
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43In a cross-coupled NAND gate latch, the output is connected to:
A.One input of the gate.
B.The output of the gate.
C.The Set input.
D.The ground.
Correct Answer: One input of the gate.
Explanation:Cross-coupling means the output of one gate () is fed back as an input to the other gate (producing ), and vice versa.
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44When converting SR to T flip-flop, the equations derived are:
A.
B.
C.
D.
Correct Answer:
Explanation:For Toggle (): If , we need Set (). If , we need Reset (). This logic maps to and .
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45The standard symbol for a clock input with a 'Dynamic Indicator' (triangle) but no bubble represents:
A.Active High Level Trigger
B.Active Low Level Trigger
C.Positive Edge Trigger
D.Negative Edge Trigger
Correct Answer: Positive Edge Trigger
Explanation:The triangle indicates edge triggering, and the absence of a bubble indicates positive (rising) edge.
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46Why are asynchronous inputs (Preset/Clear) often active low?
A.Because TTL logic handles low signals better.
B.To prevent accidental activation by noise (which is often high spikes).
C.It is just a manufacturing standard.
D.Because they are connected to ground.
Correct Answer: Because TTL logic handles low signals better.
Explanation:While noise immunity is a factor, historically in TTL logic, unconnected inputs float high, so active low inputs are safer (won't activate if disconnected) and easier to drive with open-collector outputs.
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47What is Metastability in flip-flops?
A.A state where the output is strictly 0.
B.An unstable state occurring if Setup/Hold times are violated, where output hovers between 0 and 1.
C.The state when Clock is High.
D.A feature used for random number generation.
Correct Answer: An unstable state occurring if Setup/Hold times are violated, where output hovers between 0 and 1.
Explanation:Metastability occurs when data changes too close to the clock edge, leaving the internal latch balanced between logic levels for an unpredictable time.
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48Consider a JK flip-flop. If , which input combination results in ?
A.
B.
C.
D.
Correct Answer:
Explanation:To change from 1 to 0, we can Reset ($0,1$) or Toggle ($1,1$). However, from the options provided, (Reset) is the only one that guarantees $0$.
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49What happens if the clock pulse width is greater than the propagation delay of the flip-flop in a level-triggered JK flip-flop?
A.Normal operation
B.Race-around condition
C.Metastability
D.Output holds indefinitely
Correct Answer: Race-around condition
Explanation:If the level-triggered clock stays active longer than the propagation delay, the toggled output feeds back to the input while the clock is still active, causing multiple toggles.
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50Which flip-flop has no 'No Change' condition in its standard truth table (excluding Enable control)?
A.SR Flip-Flop
B.JK Flip-Flop
C.D Flip-Flop
D.T Flip-Flop
Correct Answer: D Flip-Flop
Explanation:In a standard D flip-flop truth table, output always follows D (0 or 1). There is no combination of D that commands 'Hold previous state' explicitly without manipulating the clock/enable.