Back to Subject

Unit 3 - Practice Quiz

ECE213 50 Questions
0 Correct 0 Wrong 50 Left
0/50

1 Which of the following statements characterizes a combinational logic circuit?

A. The output depends only on the present input values.
B. The output depends on present inputs and past output states.
C. It requires a clock signal to operate.
D. It contains memory elements like flip-flops.

2 In a Half Adder circuit, what is the boolean expression for the Carry output () given inputs and ?

A.
B.
C.
D.

3 How many inputs and outputs does a Full Adder have?

A. 2 inputs, 2 outputs
B. 3 inputs, 2 outputs
C. 3 inputs, 3 outputs
D. 2 inputs, 1 output

4 The Sum output () of a Full Adder with inputs and is given by:

A.
B.
C.
D.

5 Which of the following logic circuits can be used to implement a Full Adder?

A. One Half Adder and one OR gate
B. Two Half Adders and one OR gate
C. Two Half Adders and one AND gate
D. Two OR gates and two AND gates

6 In a Half Subtractor, the boolean expression for the Difference () is same as:

A. The Carry in a Half Adder
B. The Sum in a Half Adder
C. The Borrow in a Half Subtractor
D. The Output of a NOR gate

7 What is the boolean expression for the Borrow output () of a Half Subtractor subtracting from ()?

A.
B.
C.
D.

8 The main disadvantage of a Ripple Carry Adder is:

A. It requires too many gates.
B. It consumes high power.
C. The propagation delay increases linearly with the number of bits.
D. It cannot perform subtraction.

9 Which adder design is used to reduce the carry propagation delay found in parallel adders?

A. Ripple Carry Adder
B. Look-Ahead Carry Adder
C. Serial Adder
D. Half Adder

10 A digital magnitude comparator compares two binary numbers and . Which logic gate represents the equality output () for a single bit?

A. XOR
B. XNOR
C. NAND
D. AND

11 A Multiplexer (MUX) is also known as a:

A. Data Distributor
B. Data Selector
C. Encoder
D. Decoder

12 If a Multiplexer has selection lines, how many maximum input lines can it support?

A.
B.
C.
D.

13 How many selection lines are required for an 8-to-1 Multiplexer?

A. 1
B. 2
C. 3
D. 8

14 Which combinational circuit is used to convert parallel data into serial data?

A. Decoder
B. Demultiplexer
C. Multiplexer
D. Comparator

15 A Demultiplexer is effectively a:

A. Many-to-one switch
B. One-to-many switch
C. Code converter
D. Parity generator

16 A 1-to-4 Demultiplexer can be implemented using:

A. A 2-to-4 Decoder with the enable input acting as the data input.
B. A 4-to-1 Multiplexer.
C. A 4-bit Encoder.
D. Two Half Adders.

17 A Decoder with input lines can have a maximum of _____ output lines.

A.
B.
C.
D.

18 Which circuit is primarily used for address decoding in memory systems?

A. Encoder
B. Decoder
C. Multiplexer
D. Adder

19 What is the function of an Encoder?

A. Convert binary code to decimal
B. Convert an active input signal into a coded binary output
C. Select one output from multiple inputs
D. Compare two binary numbers

20 In a Priority Encoder, if two or more inputs are active simultaneously, what happens?

A. The output becomes undefined.
B. The circuit burns out.
C. The input with the highest priority is encoded.
D. The input with the lowest priority is encoded.

21 A Decimal-to-BCD encoder has inputs and outputs.

A. 4 inputs, 10 outputs
B. 10 inputs, 4 outputs
C. 16 inputs, 4 outputs
D. 8 inputs, 3 outputs

22 Which logic gate is best suited for designing a Parity Generator/Checker?

A. NAND
B. NOR
C. XOR
D. AND

23 An even parity generator produces a '1' output when:

A. The total number of 1s in the input is even.
B. The total number of 1s in the input is odd.
C. All inputs are 0.
D. All inputs are 1.

24 Which of the following describes 'Fan-out' in logic families?

A. The time taken for the output to change state.
B. The number of logic gates on a single chip.
C. The maximum number of standard load inputs a logic gate output can drive.
D. The power dissipated by the gate.

25 The 'Noise Margin' of a logic family refers to:

A. The maximum frequency of operation.
B. The ability of the logic circuit to tolerate extraneous voltage fluctuations.
C. The minimum power required to operate.
D. The delay between input and output.

26 Which Figure of Merit is used to compare different logic families?

A. Fan-in Fan-out
B. Propagation Delay Power Dissipation
C. Noise Margin Voltage
D. Supply Voltage Current

27 TTL stands for:

A. Transistor-Transistor Logic
B. Transistor-Transformer Logic
C. Transistor-Time Logic
D. Three-Transistor Logic

28 The input stage of a standard TTL NAND gate typically contains:

A. A MOSFET.
B. A multi-emitter transistor.
C. A Zener diode.
D. A capacitor.

29 Which output configuration in TTL allows for 'Wired-AND' connections?

A. Totem-Pole Output
B. Open Collector Output
C. Tri-state Output
D. Push-Pull Output

30 What is the primary advantage of the 'Totem-Pole' output configuration in TTL?

A. It allows Wired-AND connections.
B. It reduces power consumption to zero.
C. It provides high operating speed and high fan-out capability.
D. It reduces the number of transistors.

31 Why should Totem-Pole outputs never be connected together?

A. It causes a short circuit resulting in high current damage.
B. It creates a high impedance state.
C. It reduces the noise margin.
D. It slows down the circuit.

32 An unconnected (floating) input in a standard TTL gate acts as a logic:

A. Low (0)
B. High (1)
C. Undefined
D. Oscillating

33 MOS logic families rely primarily on which component?

A. Bipolar Junction Transistors (BJT)
B. Field Effect Transistors (FET)
C. Diodes
D. Vacuum Tubes

34 CMOS stands for:

A. Complex Metal Oxide Semiconductor
B. Complementary Metal Oxide Semiconductor
C. Capacitive Metal Oxide Semiconductor
D. Charged Metal Oxide Semiconductor

35 A CMOS inverter consists of:

A. Two NMOS transistors connected in series.
B. One NMOS and one PMOS transistor connected in series.
C. Two PMOS transistors connected in parallel.
D. One NMOS transistor and a resistor.

36 What is the primary advantage of CMOS logic over TTL?

A. Higher switching speed
B. Extremely low static power consumption
C. Higher current drive capability
D. Lower manufacturing cost

37 In a CMOS circuit, power dissipation increases significantly with:

A. Decrease in temperature
B. Increase in operating frequency
C. Decrease in supply voltage
D. Increase in load resistance

38 Which logic family typically has the highest noise margin?

A. TTL
B. ECL
C. CMOS
D. RTL

39 ECL (Emitter Coupled Logic) is best known for its:

A. Low Power Consumption
B. High Speed
C. High Noise Margin
D. High Integration Density

40 Tri-state logic devices have three states: High, Low, and _____.

A. Super High
B. High Impedance (Hi-Z)
C. Negative
D. Oscillating

41 To implement the boolean function using a Multiplexer, which MUX size is appropriate?

A. 4:1 MUX
B. 8:1 MUX
C. 2:1 MUX
D. 16:1 MUX

42 Which device allows a 7-segment display to show decimal numbers based on a 4-bit input?

A. 4:1 Multiplexer
B. BCD to 7-segment Decoder
C. Priority Encoder
D. Full Adder

43 The propagation delay of a logic gate is measured in:

A. Milliseconds (ms)
B. Microseconds (s)
C. Nanoseconds (ns)
D. Picofarads (pF)

44 In CMOS logic, the PMOS transistor is ON when the gate voltage is:

A. High (Logic 1)
B. Low (Logic 0)
C. Floating
D. Equal to Drain voltage

45 Which of the following is a Unipolar logic family?

A. TTL
B. ECL
C. DTL
D. NMOS

46 How many 3-to-8 line decoders are necessary to construct a 4-to-16 line decoder?

A. 1
B. 2
C. 3
D. 4

47 What is the equivalent resistance of a CMOS input?

A. Very Low
B. Zero
C. Very High
D. Depends on the frequency

48 Which of the following circuits can be used to compare two 4-bit numbers?

A. 7485 Magnitude Comparator
B. 7400 NAND Gate
C. 7404 Inverter
D. 7432 OR Gate

49 In a Full Subtractor, the Borrow Out expression is . What does represent?

A. Binary Input
B. Borrow from the previous lower significant position
C. Borrow sent to the next higher significant position
D. The difference bit

50 Why are CMOS devices susceptible to damage from static electricity?

A. Because of low input impedance.
B. Because of the thin oxide layer at the gate inputs.
C. Because they operate at high voltages.
D. Because they have no protection diodes.
Previous MCQ
Unit 2
Next MCQ
Unit 4