Unit 5: Introduction to Sequential Logic Circuits - Subjective Questions

A latch is a level-sensitive bistable storage element capable of storing one bit. An active-high SR latch consists of two cross-coupled NOR gates.

• S = 0, R = 0: The previous output is retained; this is the memory condition.
• S = 1, R = 0: The latch is set, so and .
• S = 0, R = 1: The latch is reset, so and .
• S = 1, R = 1: Both NOR outputs become 0. When the inputs return to 0, the final state may be unpredictable; hence this input is forbidden.

The characteristic equation, valid when , is

Here, is the present state and is the next state.

A D latch is a level-sensitive one-bit storage device having a data input and an enable input . It can be formed from an SR latch by applying to the set input and to the reset input through enable gates.

• When , the latch is transparent and follows .
• When , both effective SR inputs are inactive and the previous state is stored.

Its characteristic equation is

The forbidden SR combination is removed because the internal set and reset inputs are derived from complementary signals. Therefore, they cannot both be asserted simultaneously under normal operation.

The principal differences are:

• Sensitivity: A latch is level-sensitive, whereas a flip-flop is normally edge-triggered.
• Control: A latch responds throughout the active enable level; a flip-flop responds only at a specified clock transition.
• Complexity: Latches generally require fewer gates and can be faster, while flip-flops provide stricter timing control.
• Output behavior: A transparent latch may allow input changes to pass to the output during its active level. A flip-flop samples its input only at the triggering edge.
• Use: Latches are used in temporary storage, asynchronous control, and some high-performance pipelines. Flip-flops are used in synchronous registers, counters, state machines, and frequency dividers.

Thus, both store one bit, but they differ in how and when the stored state is updated.

A clocked SR flip-flop changes state only when its clocking condition is active. At the active clock event, its operation is:

The characteristic equation is

A clocked SR flip-flop provides synchronization, but it retains the invalid input combination . Preset and clear terminals, when provided, usually act asynchronously and override the clocked inputs.

The JK flip-flop is an improved SR flip-flop in which feedback removes the forbidden input condition. At the active clock edge:

From the table, the next state is 1 either when and , or when and . Hence,

Unlike an SR flip-flop, is valid and causes toggling. This makes the JK flip-flop versatile for counters, control circuits, and conversions to other flip-flop types.

An edge-triggered D flip-flop samples the data input only at the specified active clock edge. In a positive-edge-triggered device, is copied to at the rising edge; between edges, the output remains unchanged.

Its characteristic equation is

Important timing requirements are:

• Setup time : Minimum interval for which must remain stable before the active edge.
• Hold time : Minimum interval for which must remain stable after the edge.
• Clock-to-output delay : Time taken for to respond after the active edge.

Violation of setup or hold time can cause metastability, during which the output may temporarily fail to settle at a valid logic level.

A T flip-flop has a single input and toggles its state when . Its operation is:

The sum-of-products characteristic equation is

Equivalently,

A T flip-flop can be obtained from a JK flip-flop by connecting . Its common applications are binary counters and divide-by-two frequency dividers.

The race-around condition occurs in a level-triggered JK flip-flop when and the active clock pulse remains present longer than the propagation delay. Because the output is fed back to the inputs, toggles repeatedly while the clock is active. The state at the end of the clock pulse then becomes uncertain.

It can be eliminated by:

• Making the clock pulse width smaller than the time required for a second toggle.
• Using an edge-triggered JK flip-flop, which responds only at a clock transition.
• Using a master-slave JK flip-flop, whose master and slave operate during opposite clock phases.

The latter two methods are preferred because they ensure only one effective state change per clock cycle.

A master-slave JK flip-flop consists of two latches connected in cascade:

• The master receives the external and inputs and is enabled during one clock level.
• The slave receives the master's output and is enabled during the opposite clock level.

For a common implementation, the master accepts input while the clock is high, but the slave remains disabled. When the clock goes low, the master is disabled and the slave copies the master's stored state to the output. Thus, input sampling and output updating occur in separate phases.

When , the master determines one toggled state using the old output. The slave transfers that state only after the master has been isolated. Feedback therefore cannot cause repeated toggling during the same clock pulse, preventing race-around.

An excitation table specifies the input values required to produce a desired transition from to . Here, denotes a don't-care value.

Excitation tables are used in sequential-circuit design and flip-flop conversion. After determining required state transitions, the table gives the necessary flip-flop inputs, which can then be minimized using Boolean algebra or Karnaugh maps.

For a D flip-flop, the required next state is

The JK characteristic equation is

Choose the input connections

Substitution gives

Therefore, connecting directly to and to makes the JK flip-flop behave exactly like a D flip-flop.

The D flip-flop characteristic equation is

The desired T flip-flop equation is

Therefore, the required input to the D flip-flop is

The implementation uses an XOR gate whose inputs are and the present output ; its output drives .

• If , then , so the state is held.
• If , then , so the state toggles at the next active clock edge.

The general conversion procedure is:

1. Write the characteristic table of the required flip-flop.
2. List each present-state and input combination of the required flip-flop.
3. Determine the desired next state.
4. Use the excitation table of the available flip-flop to find its required inputs.
5. Minimize the input functions and draw the logic circuit.

For an SR-to-D conversion, a D flip-flop requires . The SR inputs must set the circuit when and reset it when . A direct valid choice is

Because and are complementary, the forbidden input never occurs. The resulting SR flip-flop copies to at the active clock event.

A shift register is a group of clocked flip-flops used to store binary data and shift it by one position on each active clock edge.

A four-bit SISO register consists of four D flip-flops connected in cascade. The serial input feeds the first stage, and each stage output feeds the next stage input. All stages share a common clock. For a right-shift register:

A bit applied at the serial input enters the first stage after one clock pulse and reaches the serial output after four clock pulses. SISO registers are used as digital delay lines and for serial data transfer.

A four-bit SIPO shift register accepts data one bit at a time and provides the stored word simultaneously at four outputs. It uses four cascaded flip-flops with a common clock.

On each active edge:

• The new serial bit enters the first stage.
• The previous first-stage bit moves to the second stage.
• The remaining stored bits shift similarly toward the last stage.

After four clock pulses, the four serially applied bits are available together at . The exact order depends on the shift direction and the order in which bits were transmitted.

Applications include serial-to-parallel conversion, receiving serial communication data, driving parallel displays, and expanding the number of output lines of a controller.

A four-bit PISO register loads an entire binary word simultaneously and then transmits it one bit at a time. A mode-control input selects one of two operations:

• Parallel-load mode: The four external data bits are applied to the respective flip-flop inputs and stored on the active clock edge.
• Shift mode: Each subsequent clock moves the stored bits by one stage, and one bit appears at the serial output.

Multiplexers or gating logic before each flip-flop select either its parallel input or the output of the preceding stage. After loading, four shift pulses are required to transmit all four bits. PISO registers are used in parallel-to-serial conversion, data transmission, and reducing the number of communication lines.

A four-bit PIPO register consists of four flip-flops with separate data inputs and outputs but a common clock. All four input bits are loaded simultaneously at the active clock edge and become available together at the outputs. It is used for temporary word storage and parallel data transfer.

Comparison:

For an -bit word, SISO, SIPO, and PISO generally require multiple shift clocks for complete transfer, whereas a PIPO register can load or present the whole word in one clock operation.

A four-bit asynchronous UP counter uses four toggle flip-flops, usually with or . The external clock drives only the least significant stage. Each following stage is clocked by the output transition of the preceding stage.

The counter follows the binary sequence

Each stage divides its input frequency by two. If the external frequency is , the stage frequencies are

Because the stages do not change simultaneously, propagation delays accumulate like a ripple. Intermediate false states can briefly appear during transitions. If each stage delay is , the approximate worst-case settling time is .

An asynchronous UP/DOWN counter is a ripple counter whose interstage clock connections can be selected to reverse the counting direction. All flip-flops operate in toggle mode.

• In UP mode, each higher-order stage is clocked by the output transition of the preceding stage that corresponds to a carry.
• In DOWN mode, it is clocked by the complementary output transition, corresponding to a borrow.

A direction-control signal and gating or multiplexing logic select either or of each stage as the clock source for the next stage. For a three-bit counter, the UP sequence is , while the DOWN sequence is . Since it is asynchronous, ripple delay limits its maximum operating frequency.

For a Mod- counter, the number of flip-flops must satisfy

For ,

so four flip-flops are required. Four toggle flip-flops are first connected as a binary ripple counter. The desired states are decimal 0 through 9, corresponding to through .

The next natural state is decimal 10, or . A decoding gate detects this state. Since the 1s occur at and , these outputs can drive a NAND gate when the asynchronous clear inputs are active-low. When appears, the decoder immediately clears all flip-flops to .

The sequence is therefore to , followed by reset to . Decoder and clear propagation delays may produce a brief transient state at .