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Unit 5: Introduction to Sequential Logic Circuits

PHY175 — Modern Physics And Electronics 10 min read

I. Foundations of Sequential Logic

Sequential logic circuits are digital circuits whose outputs depend on both the present inputs and the previously stored state. Unlike combinational circuits, they contain memory elements and commonly use clock signals to coordinate state changes.

  • Governing principle: The next state is a function of the present state and current inputs:
    TEXT
      Q(t + 1) = F[Q(t), X(t)]
  Y(t) = G[Q(t), X(t)]

    Here, Q(t) is the present state, Q(t + 1) is the next state, X(t) represents inputs, and Y(t) represents outputs.
  • Memory: A latch or flip-flop stores one binary digit, called a bit, represented by Q = 0 or Q = 1.
  • Complementary output: Many memory elements provide Q and Q̅, ideally satisfying Q̅ = NOT Q.
  • Clock convention: A clock is a periodic digital signal used to determine when a circuit may change state.
    • A latch is generally level-sensitive.
    • A flip-flop is generally edge-triggered.
  • Active levels: An input may be active-high, asserted by logic 1, or active-low, asserted by logic 0.
  • Timing requirements:
    • Setup time (tSU): Minimum time for which data must remain stable before the active clock edge.
    • Hold time (tH): Minimum time for which data must remain stable after that edge.
    • Propagation delay (tpd): Time between an input or clock transition and the resulting output transition.
  • Main classifications: Sequential circuits include storage elements, shift registers, synchronous counters, and asynchronous counters.

II. Latches — Level-Sensitive Storage Elements

A. Latch (SR and D)

A latch stores one bit and can respond throughout the active level of its control signal.

  1. SR latch

    • Construction: An active-high SR latch can be formed from two cross-coupled NOR gates; S means set and R means reset.

    • Operation:

      S R Next output Q(t+1) Function
      0 0 Q(t) Hold
      0 1 0 Reset
      1 0 1 Set
      1 1 Invalid Forbidden

    • Characteristic relation: For valid input combinations:

      TEXT
           Q(t + 1) = S + R̅Q(t)


      Here, + means OR, adjacency means AND, and R̅ means NOT R.

    • Forbidden condition: In a NOR latch, S = R = 1 forces both outputs low and may produce an unpredictable final state when both inputs return to 0.

    • NAND form: A cross-coupled NAND latch uses active-low inputs S̅ and R̅; its forbidden condition is S̅ = R̅ = 0.

  2. D latch

    • Purpose: The D latch removes the SR latch’s forbidden input combination by generating set and reset signals from one data input.
    • Inputs: D is data and E is enable.
    • Operation:
      • When E = 1, the latch is transparent and Q follows D.
      • When E = 0, it holds the previous value.
    • Characteristic relation:
      TEXT
           Q(t + 1) = ED + E̅Q(t)

      Here, E is enable and D is the data input.
    • Use: D latches appear in temporary storage, gated data paths, and register implementations.

B. Applications and Limitations

Latches provide simple storage but require careful control of input timing.

  • Applications: Switch debouncing, asynchronous control, temporary data storage, and gated memory.
  • Advantage: A latch usually requires fewer gates than an equivalent edge-triggered flip-flop.
  • Limitation: Because a D latch is transparent during its active level, unwanted input changes can pass to the output.
  • Timing risk: Violating setup or hold time can cause metastability, during which Q temporarily remains between valid logic levels.

III. Flip-Flops — Edge-Triggered Binary Memory

A. Flip-flop (SR, JK, D and T)

A flip-flop stores one bit but changes state only at a specified rising or falling clock edge.

  1. SR flip-flop

    • Operation: At the active clock edge, S = 1, R = 0 sets the output, while S = 0, R = 1 resets it.
    • Hold state: S = R = 0 preserves Q(t).
    • Restriction: S = R = 1 is forbidden in the basic SR flip-flop.
    • Characteristic equation:
      TEXT
           Q(t + 1) = S + R̅Q(t), provided SR ≠ 1

  2. JK flip-flop

    • Purpose: The JK design removes the forbidden state of the SR flip-flop.

    • Operation:

      J K Q(t+1) Function
      0 0 Q(t) Hold
      0 1 0 Reset
      1 0 1 Set
      1 1 Q̅(t) Toggle

    • Characteristic equation:

      TEXT
           Q(t + 1) = JQ̅(t) + K̅Q(t)

    • Feedback: Present outputs are fed back internally so that J = K = 1 complements the stored state.

  3. D flip-flop

    • Operation: The value at D immediately before the active clock edge becomes the next output.
    • Characteristic equation:
      TEXT
           Q(t + 1) = D
    • Advantage: A single data input gives unambiguous operation and makes the device suitable for registers.
    • Example: If D = 1 at a rising clock edge, Q becomes 1 after the propagation delay, even if D later changes between edges.

  4. T flip-flop

    • Operation: T = 0 holds the state, whereas T = 1 toggles it at each active clock edge.
    • Characteristic equation:
      TEXT
           Q(t + 1) = T ⊕ Q(t)

      Here, ⊕ denotes XOR.
    • Frequency division: With T = 1, the output frequency is half the clock frequency, fQ = fCLK/2.
    • Use: T flip-flops are fundamental building blocks of binary counters.

B. Control Inputs and Timing

Flip-flops may include additional inputs that operate independently of the clock.

  • Preset: An asynchronous preset forces Q = 1.
  • Clear: An asynchronous clear forces Q = 0.
  • Priority: Preset and clear normally override clocked inputs, but asserting both may be prohibited.
  • Edge symbols: A triangle at the clock input denotes edge triggering; an added bubble denotes falling-edge triggering.
  • Limitation: Excessive clock skew or setup-and-hold violations can produce incorrect or metastable states.

IV. Master-Slave Storage

A. Master-slave flip-flop

A master-slave flip-flop uses two latches in cascade, enabled on opposite clock levels, so the external output changes only once per clock cycle.

  • Master stage: For one clock level, the master accepts and stores the input while the slave remains disabled.
  • Slave stage: At the opposite clock level, the master closes and the slave copies the master’s stored state.
  • Two-phase action:
    1. With CLK = 1 in a common arrangement, the master is active and the slave holds its output.
    2. When CLK becomes 0, the master holds and the slave updates Q.
  • Race-around prevention: In a level-triggered JK circuit with J = K = 1, repeated toggling can occur if the clock pulse is wider than the propagation delay. Master-slave isolation permits only one externally visible toggle per cycle.
  • Effective triggering: Depending on latch polarity, the complete device behaves like a rising-edge or falling-edge flip-flop.
  • Trade-off: Two stages increase circuit complexity and propagation delay compared with a single latch.

V. Flip-Flop Transformation

A. Conversion of basic flip-flop

Flip-flop conversion determines the input logic required to make one available flip-flop imitate another type.

  • Conversion procedure:
    1. Write the desired flip-flop’s present-state and next-state table.
    2. Use the available flip-flop’s excitation table to find the required inputs.
    3. Minimize each input expression using Boolean algebra or Karnaugh maps.
    4. Connect combinational logic to generate those inputs.

  • Excitation requirements:

    Transition SR inputs JK inputs D input T input
    0 → 0 S=0, R=X J=0, K=X 0 0
    0 → 1 S=1, R=0 J=1, K=X 1 1
    1 → 0 S=0, R=1 J=X, K=1 0 1
    1 → 1 S=X, R=0 J=X, K=0 1 0

    Here, X means “don’t care.”

  • JK-to-D conversion: Requiring Q(t+1) = D gives:
    TEXT
      J = D
  K = D̅
  • D-to-T conversion: Since a T flip-flop must hold for T = 0 and toggle for T = 1:
    TEXT
      D = T ⊕ Q(t)
  • JK-to-T conversion:
    TEXT
      J = T
  K = T
  • Significance: Conversion allows a design to use available integrated circuits while preserving the required state behavior.

VI. Shift Registers — Clocked Data Movement

A. Operation of basic shift registers (SISO, SIPO, PISO, PIPO)

A shift register is a chain of flip-flops that stores a binary word and transfers data serially, in parallel, or both.

  1. SISO: Serial-In Serial-Out

    • Operation: One bit enters the first stage per clock pulse, and stored bits move one position toward the serial output.
    • Delay: In an n-stage SISO register, a bit requires n active clock edges to travel from input through all stages.
    • Use: Digital delay lines and serial data transfer.

  2. SIPO: Serial-In Parallel-Out

    • Operation: Bits enter serially but are read simultaneously from all flip-flop outputs.
    • Example: Loading a four-bit word requires four clock pulses; the four outputs then represent the complete word.
    • Use: Serial-to-parallel conversion, such as expanding a serial communication line into multiple outputs.

  3. PISO: Parallel-In Serial-Out

    • Operation: A load control places all input bits into the register simultaneously; later clock pulses shift them out one at a time.
    • Control modes: LOAD selects parallel loading, while SHIFT selects serial movement.
    • Use: Parallel-to-serial conversion and data transmission.

  4. PIPO: Parallel-In Parallel-Out

    • Operation: All bits are loaded together on an active clock edge and are available together at the outputs.
    • Movement: It functions primarily as a storage or transfer register rather than a serial shifter.
    • Use: Buffering binary words between digital subsystems.

B. Register Characteristics

Shift-register performance is determined by its capacity, clock rate, and data organization.

  • Capacity: A register containing n flip-flops stores an n-bit word.
  • Direction: Shift registers may shift right, shift left, or operate bidirectionally.
  • Timing: All stages commonly share one clock, making ordinary shift registers synchronous.
  • Applications: Data conversion, temporary storage, sequence generation, arithmetic shifting, and communication interfaces.

VII. Ripple Counting

A. Asynchronous counter (UP/DOWN/Mod-N)

An asynchronous or ripple counter clocks only its first flip-flop directly; each later stage is triggered by the output of the preceding stage.

  • Ripple operation: State changes propagate stage by stage rather than occurring simultaneously.
  • Binary capacity: A counter with n flip-flops has up to:
    TEXT
      Number of states = 2^n
  • Frequency division: Each toggling stage divides its input frequency by two:
    TEXT
      fn = fCLK / 2^n

    Here, fn is the frequency at stage n, and fCLK is the external clock frequency.

  1. UP counter

    • Sequence: A three-bit binary UP counter follows 000, 001, 010, 011, 100, 101, 110, 111, then repeats.
    • Interpretation: The least significant bit toggles every clock pulse; each higher bit toggles at half the preceding bit’s frequency.
    • Hardware: T flip-flops with T = 1, or JK flip-flops with J = K = 1, provide toggle action.

  2. DOWN counter

    • Sequence: A three-bit DOWN counter follows 111, 110, 101, 100, 011, 010, 001, 000.
    • Direction control: The clock connection may use either Q or Q̅, depending on flip-flop triggering polarity.
    • UP/DOWN selection: Logic gates or multiplexers select the appropriate output path to determine counting direction.

  3. Mod-N counter

    • Definition: A modulus-N counter passes through exactly N states before returning to its initial state.
    • Required stages:
      TEXT
           n = ceil(log2 N)

      Here, n is the number of flip-flops and ceil means rounding upward.
    • Example: A Mod-10 counter requires four flip-flops because 2^3 < 10 ≤ 2^4; decoding binary 1010 can asynchronously clear the counter to 0000.
    • Truncated sequence: When N < 2^n, reset logic prevents unused states from forming part of the normal count.

B. Advantages and Limitations

Asynchronous counters are economical but become less reliable at high speed.

  • Advantage: Their hardware is simple because only the first stage receives the external clock.
  • Propagation delay: For n stages, the worst-case settling time is approximately:
    TEXT
      ttotal ≈ n × tpd
  • Transient states: Outputs do not change simultaneously, so decoding logic may briefly observe false intermediate counts.
  • Applications: Low-speed event counting, clock division, timers, and simple frequency counters.
  • Limitation: High-speed or precisely decoded systems generally require synchronous counters, whose flip-flops share a common clock.
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