Unit 5: Introduction to Sequential Logic Circuits - Practice Quiz

1 What does the letter S represent in an SR latch?

2 For an active-high NOR-based SR latch, which input combination holds the previous output?

3 What is the main advantage of a D latch over an SR latch?

4 Which flip-flop removes the invalid state of the SR flip-flop?

5 What happens to a JK flip-flop when and ?

6 For a D flip-flop, what is the next output after the active clock edge?

7 What does a T flip-flop do when ?

8 Which flip-flop is commonly used to store one bit of input data directly?

9 A master-slave flip-flop is formed using how many connected flip-flop stages?

10 What is a main purpose of the master-slave arrangement in a JK flip-flop?

11 To make a JK flip-flop behave like a T flip-flop, how are its inputs connected?

12 How can a D flip-flop be made to operate as a T flip-flop?

13 What does SISO stand for in shift registers?

14 Which shift register converts serial input data into parallel output data?

15 Which shift register is used to convert parallel data into serial data?

16 In which register are data loaded and read out in parallel?

17 Why is an asynchronous counter also called a ripple counter?

18 What sequence does a 3-bit binary UP counter follow after ?

19 What sequence does a 3-bit binary DOWN counter follow after ?

20 How many distinct states does a Mod-10 counter have?

21 An active-high SR latch initially has . The input sequence is , followed by , and then . What is the final value of ?

22 A gated D latch is transparent when its enable input . If changes from to while , and later changes to while remains , what happens to ?

23 A D latch is implemented from an active-high SR latch using and . What is the main purpose of this connection?

24 A positive-edge-triggered JK flip-flop has and initially . What is after five active clock edges?

25 A positive-edge-triggered D flip-flop initially has . The value of is just before the first clock edge, changes to between edges, and is just before the second edge. What are the values of immediately after the two edges?

26 A T flip-flop starts with . Its input values at four successive active clock edges are . What is the final value of ?

27 For a JK flip-flop, the present state is . Which input pair produces the next state without relying on the toggle operation?

28 In a master-slave JK flip-flop, the master is enabled during the high clock level and the slave during the low clock level. When does the external output normally update?

29 Why does a master-slave JK flip-flop avoid the race-around problem when ?

30 A JK flip-flop is to operate as a D flip-flop. Which input connections provide ?

31 A D flip-flop is to behave as a T flip-flop. Which expression should be applied to its D input?

32 A JK flip-flop is configured as a T flip-flop by connecting . If for six active clock edges and the initial state is , what is the final state?

33 A 4-bit SISO right-shift register is initially . The serial input sequence is applied over four clock pulses, with each new bit entering the leftmost stage. What is the register content after the fourth pulse?

34 A 5-bit SIPO register starts cleared. How many clock pulses are required before all five bits of a serial word are simultaneously available at its parallel outputs?

35 A 4-bit PISO register is parallel-loaded with . It then shifts right, with used as the serial output. Which bit sequence is transmitted first through fourth?

36 Which register is most suitable for transferring an 8-bit word between two devices in one clock event when all eight data lines are available?

37 A 4-bit asynchronous binary up counter initially contains . What state does it reach after three input clock pulses?

38 A 3-bit asynchronous down counter is in state . What is its state after one more clock pulse?

39 What is the minimum number of flip-flops required to construct an asynchronous Mod-10 counter?

40 A 4-bit asynchronous counter must operate as a Mod-12 up counter by clearing when a selected state is detected. Which binary state should trigger the asynchronous clear?

41 An active-low NAND SR latch is initially in the state . Its inputs are driven to and are then returned to at exactly the same nominal time. What can be concluded about the final state?

42 A positive-level D latch initially has . Its enable is high during and . The input changes to at , respectively. Assuming negligible propagation delay, at which times does change?

43 A positive-edge-triggered JK flip-flop starts with . The values of at four successive active edges are , , , and . What is the state sequence immediately after these edges?

44 For an SR flip-flop, the inputs are generated as and . The forbidden input condition is therefore avoided. What state operation does the circuit perform?

45 A D flip-flop has and initially . At four successive active edges, is , , , and . What is the state sequence after the four edges?

46 A T flip-flop begins with . During seven successive active edges, only when the edge number is prime. What is immediately after the seventh edge?

47 A master-slave JK flip-flop uses a master latch transparent while the clock is high and a slave latch transparent while the clock is low. If throughout one complete clock pulse and initially , what happens?

48 A master-slave D flip-flop has a master latch transparent for and a slave latch transparent for . The input changes from to shortly after a rising clock transition and remains . Ignoring setup or hold violations, when can this new value first appear at ?

49 A JK flip-flop must behave exactly as a D flip-flop for every present state. Which input connections provide the required conversion?

50 A D flip-flop is used to reproduce the behavior of a JK flip-flop. Which Boolean expression must drive ?

51 An SR flip-flop is to be converted into a T flip-flop without ever applying the forbidden condition . Which excitation equations are correct?

52 A 4-bit SISO register is ordered as . Serial data enters , each stage shifts toward , and serial output is taken from before each shift. Starting from , the input bits are applied. What are the emitted bits and final state?

53 A 4-bit SIPO register initially contains . New bits enter , and existing bits shift toward . If the serial input sequence is , what parallel word is present after the third clock?

54 A 4-bit PISO register is parallel-loaded with . It then shifts toward , outputs the old before each shift, and inserts into . After three shift pulses, what has been emitted and what state remains?

55 Two edge-triggered 4-bit PIPO registers, and , share a clock. Initially and . At the first edge, both load enables are active: loads external data , while loads the output of . At the second edge, only is enabled. What are after the second edge?

56 A 4-bit asynchronous binary DOWN counter starts at . Assuming every count transition has fully settled, what state is present after 11 input pulses?

57 A 4-bit asynchronous decade counter is cleared as soon as the decoded state occurs. Which issue is most directly associated with this asynchronous decoding method?

58 Each flip-flop in a 4-bit ripple counter has a worst-case propagation delay of . The decoded output must remain stable for at least before the next input edge. What is the approximate maximum input frequency?

59 A modulus-12 asynchronous UP counter uses four flip-flops and cycles through states to . If its most significant output is observed, what fraction of each complete count cycle is high?

60 In a negative-edge-triggered asynchronous UP counter, each stage is clocked by the output of the preceding stage. During the transition from stable count to stable count , which sequence of transient states can occur because of propagation delays?