Unit 4: Introduction to Combinational Logic Circuits - Subjective Questions

Definition: A combinational logic circuit is a digital circuit whose output depends only on the present values of its input variables.

Characteristics:

• It does not contain memory elements or feedback paths.
• Its output changes whenever the input combination changes, after a propagation delay.
• It can be represented using Boolean expressions, truth tables, and logic diagrams.
• Examples include adders, subtractors, multiplexers, decoders, encoders, and comparators.

Difference from a sequential circuit:

• In a combinational circuit, output depends only on present inputs: .
• In a sequential circuit, output depends on present inputs and the previous state: .
• Sequential circuits require memory elements such as flip-flops, whereas combinational circuits do not.

Definition: A half adder adds two one-bit binary numbers, and .

The outputs are Sum and Carry .

Truth table:

Boolean expressions:

• Sum:
• Carry:

Implementation:

• An XOR gate produces the Sum output.
• An AND gate produces the Carry output.

A half adder cannot add an input carry from a previous lower-order bit.

A full adder adds three one-bit inputs: two significant bits and , and an input carry . It produces a Sum and an output carry .

Truth table:

Boolean expressions:

A full adder can be constructed using two half adders and one OR gate.

A 4-bit parallel binary adder adds two 4-bit numbers, and .

Construction:

• Four full adders are connected in cascade.
• The least significant full adder receives , , and the initial carry .
• Its output carry becomes the input carry of the next full adder.
• This connection continues up to the most significant bit.
• The final carry is denoted by .

The outputs are and the final carry .

Ripple-carry delay:
The carry generated at the least significant stage must propagate through each subsequent full adder before the final result becomes valid. Therefore, the total propagation delay increases with the number of bits. This is called ripple-carry delay and makes the parallel adder slower for large word lengths.

A half subtractor subtracts one one-bit binary number from another one-bit number . It has two outputs: Difference and Borrow .

Truth table:

Boolean expressions:

• Difference:
• Borrow:

Implementation:

• An XOR gate generates the Difference output.
• An inverter followed by an AND gate generates the Borrow output.

A half subtractor does not accept a borrow input from a lower-order stage.

A full subtractor subtracts two bits while considering a borrow input from the previous lower-order position. Its inputs are , , and , and its outputs are Difference and Borrow-out .

Difference expression:

Borrow-out expression:

Operation:

• represents the result of subtracting and from .
• becomes 1 whenever the subtraction requires a borrow from the next higher-order position.

A full subtractor may be constructed using two half subtractors and an OR gate. The first half subtractor subtracts from , and the second subtracts from the first Difference output.

Applications:

• Half adders are used in simple arithmetic circuits and as building blocks for full adders.
• Full adders are cascaded to form parallel binary adders, arithmetic logic units, and processor arithmetic circuits.

A multiplexer, or MUX, is a data selector that transfers one of several input signals to a single output line. Selection is controlled by select lines.

A 4-to-1 multiplexer has four data inputs , , , and , two select lines and , and one output .

Truth table:

Boolean expression:

A multiplexer is used in data routing, communication systems, and implementation of Boolean functions.

A multiplexer can implement a Boolean function by using some variables as select lines and connecting the data inputs to logic 0, logic 1, or remaining variables.

General procedure:

• Determine the number of variables in the Boolean function.
• Select variables as select lines for a -to-1 multiplexer.
• Prepare the truth table of the function.
• For each select-line combination, determine whether the corresponding data input must be connected to 0, 1, a remaining variable, or its complement.
• Connect the data inputs accordingly and take the MUX output as the function output.

For example, if a 4-to-1 MUX uses and as select lines, each data input is assigned according to the values of the function for the corresponding combinations and .

This method reduces the amount of separate logic needed to realize a Boolean function.

A de-multiplexer, or DEMUX, is a data distributor that transfers one input signal to one of several output lines according to the select-line combination.

A 1-to-4 de-multiplexer has one data input , select lines and , and four outputs , , , and .

Truth table:

All unselected outputs remain 0 when the input is enabled.

Output equations:

De-multiplexers are used in data distribution, address decoding, and communication systems.

Both circuits use select lines. For select lines, a multiplexer can select one of inputs, while a de-multiplexer can route the input to one of outputs.

A decoder is a combinational circuit that converts an -bit binary input into one of mutually exclusive output lines. For each input combination, exactly one output is activated, assuming an active-high enabled decoder.

A 2-to-4 decoder has inputs and and outputs , , , and .

Truth table:

Output equations:

A decoder is used in memory addressing, instruction decoding, display systems, and code conversion.

The enable input controls whether a decoder is active or disabled.

For an active-high enable input :

• When , all outputs are inactive regardless of the input values.
• When , the decoder operates normally and activates one output according to the binary input .

The output equations are:

The enable input allows several decoders to be combined and is also useful for selecting a particular memory chip or circuit section. In practical ICs, the enable input may be active-low, in which case the operating conditions are reversed.

An encoder is a combinational circuit that converts one active input out of several input lines into a corresponding binary code at its output.

A 4-to-2 encoder has four input lines , , , and , and two output lines and .

Truth table:

Only one input should be active at a time in a basic encoder.

Output equations:

Encoders are used in keyboards, digital systems, and data compression interfaces.

An ordinary encoder assumes that only one input is active at a time. If multiple inputs become active simultaneously, its output may be ambiguous or invalid.

A priority encoder assigns a priority level to each input. When several inputs are active, it produces the binary code of the highest-priority active input.

Comparison:

• An ordinary encoder operates correctly only for one active input.
• A priority encoder can handle multiple active inputs.
• A priority encoder includes additional logic to determine the highest-priority input.
• It often provides a valid or enable output to indicate that at least one input is active.

For a 4-input priority encoder, if has the highest priority, then is encoded whenever it is 1, even if , , or are also 1. Priority encoders are used in interrupt controllers and resource arbitration circuits.

A magnitude comparator compares two binary inputs and and produces three outputs: for , for , and for .

Truth table:

Output expressions:

Only one of the three outputs is high for any input combination.

A 2-bit comparator compares with . The most significant bits are compared first. The least significant bits are considered only when the most significant bits are equal.

Define:

Logic expressions:

• :
• :
• :

Operating principle:

• If and , then .
• If and , then .
• If , the comparison depends on and .
• Equality occurs only when both corresponding bit pairs are equal.

The three outputs are mutually exclusive.

A decoder activates one output corresponding to the applied input code. An encoder performs the reverse operation, provided that only one input is active or priority logic is included.

A full adder can be constructed in three stages.

Stage 1: The first half adder adds and .

• Intermediate sum:
• Intermediate carry:

Stage 2: The second half adder adds and .

• Final Sum:
• Second carry:

Stage 3: The two carry outputs are ORed.

Substituting the intermediate expressions gives:

Using Boolean expansion, the carry expression is also written as:

Binary subtraction can be performed using an adder by representing the subtrahend in 2's complement form.

To calculate :

• Complement every bit of to obtain its 1's complement.
• Add 1 to obtain the 2's complement of .
• Add this result to using a binary adder.
• If an end carry is produced, it is discarded and the remaining bits represent a positive result.
• If no end carry is produced, the result is negative and is represented in 2's complement form.

Mathematically:

A parallel adder-subtractor can perform both operations by conditionally complementing each bit of and selecting the initial carry according to the required operation.