Unit 5: Sequential Logic Circuits Applications - Subjective Questions

A shift register is a group of flip-flops connected in a chain such that the output of one flip-flop becomes the input of the next. It is used to store and shift binary data.

Basic Operation:

• Each clock pulse shifts the stored bits by one position (left or right).
• Data is entered serially or in parallel and retrieved serially or in parallel.

Four Types Based on Data Movement:

1. Serial-In Serial-Out (SISO): Data enters and exits one bit at a time.
2. Serial-In Parallel-Out (SIPO): Data enters serially, all bits available simultaneously at outputs.
3. Parallel-In Serial-Out (PISO): All bits loaded at once, output taken serially.
4. Parallel-In Parallel-Out (PIPO): Data loaded and read in parallel simultaneously.

Shift registers are commonly built using D flip-flops and are used for data storage, data transfer, and serial-parallel conversion.

A SISO shift register accepts data serially (one bit per clock pulse) and outputs data serially.

Construction:

• Uses D flip-flops connected in cascade.
• Output of one flip-flop feeds the input of the next.

Structure:

Data_in -> [D FF0] -> [D FF1] -> [D FF2] -> [D FF3] -> Data_out
^ ^ ^ ^
CLK--------CLK--------CLK--------CLK

Working:

• On each clock edge, the bit at the input is shifted into FF0, and each stored bit moves one position toward the output.
• For a 4-bit register, it takes 4 clock pulses to shift one bit from input to output.

Example: To load 1011, four clock pulses are needed. To read out the data, four more clock pulses are required.

Application: Used for time delay and serial data transfer between systems.

Summary: Asynchronous counters are simpler but slower, while synchronous counters are faster and more reliable at the cost of extra logic.

A 3-bit synchronous up counter counts from to (0 to 7) with all flip-flops clocked simultaneously.

Count Sequence:

JK Flip-Flop Excitation:

• (LSB) toggles every clock:
• toggles when :
• toggles when :

Input Equations:

Circuit:

• FF0: tied to logic 1.
• FF1: connected to .
• FF2: connected through an AND gate of and .

All flip-flops share the same clock, ensuring synchronous operation.

A Ring Counter is a circular shift register in which the output of the last flip-flop is fed back to the input of the first flip-flop.

Working:

• It is initialized (preset) with a single 1 (e.g., ).
• On each clock pulse, the 1 circulates through the flip-flops.

State Sequence (4-bit):

Number of Valid States:

• An -bit ring counter has exactly valid states.

Characteristics:

• No decoding gates required (each state directly indicates the count).
• Inefficient use of flip-flops: flip-flops give only states (compared to in binary counters).

Application: Used in sequencing operations, timing signal generation, and controlling stepper motors.

A Johnson Counter is a modified ring counter where the complemented output () of the last flip-flop is fed back to the input of the first flip-flop.

Working:

• Starting from , the inverted feedback fills the register with 1s, then clears them.

State Sequence (4-bit):

Number of States:

• An -bit Johnson counter produces states.

Comparison with Ring Counter:

• Ring counter: states
• Johnson counter: states (twice as efficient)

Characteristics:

• Requires simple 2-input decoding gates.
• Self-starting versions require correction logic to avoid invalid states.

Application: Frequency division, generating timing sequences, and creating multi-phase clocks.

A MOD-8 asynchronous counter counts from to (8 states) and requires 3 flip-flops since .

Construction:

• Three T flip-flops with (toggle mode).
• Clock applied only to FF0; output of each FF clocks the next.

Structure:

CLK -> [T FF0] Q0 -> CLK of [T FF1] Q1 -> CLK of [T FF2] Q2

Operation:

• FF0 toggles on every clock pulse.
• FF1 toggles when makes a transition.
• FF2 toggles when makes a transition.

Count Sequence:

Limitation: Propagation delays ripple through, so the total delay is , limiting maximum frequency.

A Bidirectional Shift Register can shift data in both directions — left-to-right and right-to-left — depending on a control signal.

Direction Control:

• A mode control input (e.g., or ) selects the shift direction.
  • : Shift Right (data moves from FF0 towards FFn)
  • : Shift Left (data moves from FFn towards FF0)

Implementation:

• Each flip-flop's input is fed through multiplexers (2:1 MUX) or AND-OR logic gates.
• The MUX selects either the left-neighbor output or the right-neighbor output based on the mode control.

Logic for each stage:

Application:

• Arithmetic shift operations (multiplication/division by 2).
• Data manipulation in CPUs and reversible data transfer.

A Universal Shift Register is capable of performing all shift and load operations — serial and parallel, in both directions.

Four Operating Modes (selected by two mode-select lines ):

Construction:

• Uses D flip-flops with a 4-to-1 multiplexer at each stage's input.
• The MUX select lines are the mode-control bits .

MUX Inputs at each stage:

1. Own output (hold)
2. Right-neighbor output (shift right)
3. Left-neighbor output (shift left)
4. Parallel data input (load)

Example IC: The 74194 is a 4-bit universal shift register.

Application: General-purpose data storage, serial-parallel conversion, and register operations in microprocessors.

Key Point: A Johnson counter provides twice as many states as a ring counter using the same number of flip-flops, making it more efficient, but decoding is slightly more complex.

A MOD-6 counter counts from to (0 to 5) and resets. It requires 3 flip-flops.

State Table:

States and are don't-cares (unused).

Using JK excitation and K-map simplification:

Explanation:

• toggles every clock.
• toggles on but is prevented at count 5 to force reset.
• sets at count 4 (when ) and resets when after count 5.

All flip-flops share a common clock for synchronous operation.

A PISO shift register loads all data bits simultaneously (in parallel) and outputs them one bit at a time (serially).

Construction:

• Uses D flip-flops with a control line (SHIFT/LOAD).
• Combinational logic (AND-OR gates) selects between parallel load and shift operation.

Structure:

P0 P1 P2 P3 (parallel inputs)
| | | |
[FF0]-[FF1]-[FF2]-[FF3] -> Serial Out

Working:

• LOAD mode (SHIFT/LOAD = 0): All four bits are loaded into the flip-flops in one clock pulse.
• SHIFT mode (SHIFT/LOAD = 1): On each subsequent clock pulse, bits shift right and appear serially at the output.

Timing: For a 4-bit register, 1 clock for loading + 3-4 clocks for shifting out.

Application: Parallel-to-serial data conversion, used in serial communication (e.g., transmitting parallel data over a single line).

In a ripple counter, each flip-flop is triggered by the previous flip-flop's output, so propagation delays accumulate.

Total Propagation Delay:
For an -bit ripple counter with each flip-flop delay :

Maximum Operating Frequency:
The clock period must be greater than the total delay:

For Synchronous Counter:
All flip-flops are clocked together, so only one flip-flop delay plus gate delay matters:

Why Ripple is Slower:

• The output is not valid until the last flip-flop has toggled.
• As increases, cumulative delay increases, reducing .
• Synchronous counters avoid this by parallel clocking.

Conclusion: Synchronous counters operate at much higher frequencies since their delay is independent of the number of stages.

A SIPO shift register accepts data serially (one bit per clock) and provides parallel outputs (all bits available simultaneously).

Construction:

• Cascaded D flip-flops.
• Each flip-flop output is available as a parallel output tap.

Structure:

Data_in -> [FF0] -> [FF1] -> [FF2] -> [FF3]
|Q0 |Q1 |Q2 |Q3
(parallel outputs)

Working:

• Serial data is shifted in bit by bit on each clock pulse.
• After clock pulses, the -bit word is fully loaded and available at all outputs simultaneously.

Example: To output 1011 in parallel, four clock pulses are applied to shift the bits in.

Application:

• Serial-to-parallel conversion, used in receiving serial data (e.g., from UART) and presenting it in parallel form to a processor.

A decade counter counts from to (0 to 9) and then resets to . It requires 4 flip-flops ().

Basic Design:

• Start with a 4-bit ripple counter using T flip-flops (each ).
• Normally it would count 0–15; we must force a reset after count 9.

Reset Logic:

• Count 10 = (i.e., ).
• As soon as the count reaches , a NAND gate detects and produces a CLEAR signal.
• This clear signal resets all flip-flops to .

Reset Equation:

Operation:

Note: The state appears momentarily (a glitch) before reset. This is a limitation of asynchronous clearing.

Application: Used in digital clocks, frequency counters, and BCD counting.

A self-starting counter is one that, regardless of its initial (possibly invalid) state, will eventually enter and follow the correct counting sequence.

Problem with Ring and Johnson Counters:

• These counters use only a subset of all possible states.
  • Ring counter: valid states out of .
  • Johnson counter: valid states out of .
• If the counter powers up in an invalid state, it may get stuck in an unused loop and never reach the correct sequence.

Correction Logic:

• Additional gates are added to steer invalid states back into the valid sequence.
• Johnson Counter Correction Example: The feedback into the first flip-flop is modified as:
  
• This ensures that if an illegal state occurs, the next transitions bring it into the valid cycle.

Conclusion: Self-starting/self-correcting logic guarantees reliable operation even after power-up glitches or noise.

A basic shift register can be converted into two types of counters simply by changing the feedback connection from the last flip-flop to the first.

1. Ring Counter (Direct Feedback):

• Connect of the last flip-flop back to the input of the first flip-flop.
  
• Preset one flip-flop to 1: e.g., .
• The single 1 circulates: .
• States = .

2. Johnson Counter (Inverted Feedback):

• Connect of the last flip-flop back to the input of the first flip-flop.
  
• Starting from :
• States = .

Summary:

• Non-inverted feedback → Ring counter.
• Inverted (twisted) feedback → Johnson counter.

This demonstrates the versatility of shift registers in building sequential counting circuits.

Applications of Counter:

1. Digital clocks and timers.
2. Frequency division and event counting.

Applications of Shift Register:

1. Serial-to-parallel and parallel-to-serial data conversion.
2. Temporary data storage and delay lines.

Key Point: A counter emphasizes sequencing/counting, while a shift register emphasizes data movement/storage.

A 3-bit synchronous down counter counts from down to and repeats, with all flip-flops sharing a common clock.

Count Sequence:

Analysis of Toggle Conditions:

• toggles on every clock pulse.
• toggles when (i.e., ).
• toggles when AND (i.e., ).

Input Equations (T flip-flops):

Circuit:

• FF0: tied to logic 1.
• FF1: connected to .
• FF2: fed from an AND gate of and .

Comparison with Up Counter: For an up counter, toggle conditions use outputs; for a down counter, they use complemented outputs.

Frequency Division is a key property of counters: each flip-flop in a ripple counter divides the input frequency by 2.

Principle:

• A single flip-flop in toggle mode changes state once per two input pulses, producing an output at half the input frequency.
• Cascading flip-flops divides the frequency by .

General Relation:

where is the flip-flop position (stage number).

For a MOD-16 counter (4 flip-flops) with kHz:

Conclusion: The final flip-flop () output is 1 kHz, giving an overall division by 16. This principle is used in clock generation and timing circuits.