Unit 6: Memory and Programmable Logic - Subjective Questions

Read-Only Memory (ROM) is a non-volatile memory in which data is permanently or semi-permanently stored and can only be read during normal operation, not written.

Internal Structure:

• A ROM with address input lines and output lines can store words, each of bits.
• It consists of a decoder (which selects one of the words based on the address) and an OR array/memory array that produces the stored output bits.
• The decoder generates all minterms of the input variables.

Main Types of ROM:

• Mask ROM – programmed by the manufacturer during fabrication.
• PROM (Programmable ROM) – programmed once by the user via fusible links.
• EPROM (Erasable PROM) – erasable using ultraviolet light and reprogrammable.
• EEPROM (Electrically Erasable PROM) – erasable and reprogrammable electrically.
• Flash Memory – a high-speed, block-erasable variant of EEPROM.

ROM is widely used for storing firmware, bootloaders, and fixed lookup tables.

A ROM can realize any combinational function because it internally generates all minterms of its input variables through the decoder, and the OR array can be programmed to select the required minterms for each output.

Procedure:

• Treat the inputs of the combinational circuit as the ROM address lines.
• Treat the outputs as the ROM data lines.
• Store in each memory location the truth-table output corresponding to that input combination.

Example – 2-bit binary to square converter:
Suppose inputs and we want output = .

A ROM (2 address lines, 4 data lines) stores these values. When the address is applied, the corresponding square is read out directly.

Advantage: No Boolean simplification is needed; the truth table is directly mapped into memory.

Summary:

• PROM is one-time programmable.
• EPROM needs UV light and a quartz window for erasing.
• EEPROM offers the most flexibility, allowing in-circuit electrical erasure and reprogramming, forming the basis of modern flash memory.

Static RAM (SRAM) stores each bit using a bistable latching circuit (flip-flop) and retains data as long as power is supplied, without the need for refreshing.

SRAM Cell Structure:

• A typical SRAM cell uses 6 transistors (6T cell): four transistors form two cross-coupled inverters (the storage latch), and two access transistors connect the cell to the bit lines.

  Word Line (WL)
     |

  +-------+-------+		[Access] [Access] Transistor Transistor

  BL <cross-coupled inverters> BL'

Operation:

• Write: The Word Line is activated; the desired data value is forced onto the bit lines (BL and BL'), setting the latch state.
• Read: The Word Line is activated; the latch drives its stored value onto the bit lines, sensed by a sense amplifier.
• Hold: When Word Line is inactive, the cross-coupled inverters hold the stored bit indefinitely (as long as power is on).

Characteristics:

• Fast access, no refresh needed.
• Higher cost and lower density (more transistors per bit).
• Used in cache memory and registers.

Dynamic RAM (DRAM) stores each bit as a charge on a small capacitor, controlled by a single access transistor.

DRAM Cell (1T-1C):

• Consists of one transistor and one capacitor.
• The capacitor holds the charge representing the bit (charged = 1, discharged = 0).

• The transistor acts as a switch connecting the capacitor to the bit line when the word line is active.

  Word Line ---|Gate
  | Transistor
  Bit Line ----+----| Capacitor ---- GND

Operation:

• Write: Word line ON; the bit line charges/discharges the capacitor.
• Read: Word line ON; the small stored charge is shared with the bit line and amplified by a sense amplifier. Reading is destructive, so data must be rewritten.

Why Refreshing is Needed:

• The capacitor charge leaks away over time due to leakage currents.
• To prevent data loss, the stored charge must be periodically read and rewritten (refreshed), typically every few milliseconds.

Characteristics:

• High density and low cost (only 1 transistor per bit).
• Slower than SRAM and requires refresh circuitry.
• Used as main memory (RAM) in computers.

Summary:

• SRAM is chosen where speed matters (cache), while DRAM is chosen where large capacity at low cost is needed (main memory).

A Programmable Logic Array (PLA) is a programmable device used to implement combinational logic circuits. It consists of a programmable AND array followed by a programmable OR array.

Structure:

• Input buffers/inverters: Provide both true and complement of each input.
• Programmable AND array: Generates the required product terms (any AND combination of inputs).
• Programmable OR array: Combines the selected product terms to form the required sum-of-products outputs.
• Optional output XOR gates allow programmable output polarity.

Inputs --> [Buffers/Inverters] --> [Programmable AND Array] --> Product Terms
|
[Programmable OR Array] --> Outputs

Key Point:

• Unlike ROM, the PLA does not generate all minterms — only the specific product terms required, making it more efficient for functions with few product terms.
• Both the AND and OR arrays are programmable, giving maximum flexibility.

Use: Implementing complex combinational Boolean functions in a compact form.

Step 1 – Simplify each function using K-maps.

For :

For :

Step 2 – Look for shared product terms.

• Consider using complemented output. Checking common terms: (minterm 0) appears in both.

A compact realization sharing product terms:

• Product terms: , , , , ,

Step 3 – PLA Programming Table:

Step 4 – Implementation:

• The AND array is programmed to generate the six product terms.
• The OR array connects product terms to and as marked with '1'.

This realizes both functions in a single PLA using shared hardware.

Programmable Logic Arrays (PLAs) are versatile devices used in many digital design tasks:

• Combinational Logic Implementation: Realize any sum-of-products Boolean function efficiently, especially those with many shared product terms.

• Code Converters: Implement binary-to-BCD, BCD-to-seven-segment, gray code converters, etc.

• Control Logic / Address Decoding: Used in microprocessor systems to decode addresses and generate control signals.

• Look-Up Tables and Function Generators: Implement mathematical functions and truth tables.

• Finite State Machines (with external flip-flops): The combinational next-state and output logic can be realized in a PLA.

• Replacing SSI/MSI Logic: A single PLA can replace many discrete gates, reducing chip count, board space, and cost.

• Prototyping: Quick implementation and testing of logic designs before final fabrication.

Advantages driving these uses: flexibility (both arrays programmable), reduced package count, and efficient use of shared product terms.

A Programmable Array Logic (PAL) is a programmable logic device consisting of a programmable AND array and a fixed OR array. Only the AND connections can be programmed; the OR gate connections are predetermined by the manufacturer.

Structure:

Inputs --> [Buffers/Inverters] --> [Programmable AND Array] --> [FIXED OR Array] --> Outputs

Difference from PLA:

Key Point:

• In a PAL, a fixed number of product terms is dedicated to each output OR gate.
• PALs are cheaper and faster, making them popular for many practical designs, whereas PLAs offer greater flexibility at higher cost.

Step 1 – Write the truth table / minterms:
— this is the odd-parity / XOR function of three variables.

Step 2 – Express in SOP form:

This function cannot be simplified further (each minterm is isolated in the K-map).

Step 3 – PAL Programming:

• Since a PAL has a fixed OR array, we need at least 4 product terms allocated to the output OR gate.
• Program the AND array to produce:

PAL Programming Table:

Step 4 – Realization:

• The 4 product terms are ORed together by the fixed OR gate to give .
• This works only if the PAL provides at least 4 product terms per output; otherwise, output polarity/XOR features may be used.

Detailed Comparison:

• ROM: The AND array is a fixed decoder producing all minterms; only the OR (memory) array is programmed. Best when all/most minterms are needed (lookup tables).

• PLA: Both arrays are programmable, allowing selective generation of product terms and their flexible connection to outputs. Best for functions with many shared product terms.

• PAL: Only the AND array is programmable while OR connections are fixed. This limits product-term sharing but improves speed and reduces cost.

Selection Guideline:

• Use ROM for dense truth tables, PLA for flexible multi-output SOP logic, and PAL for fast, cost-effective designs with limited product terms.

Sequential PLDs are programmable logic devices that combine combinational logic arrays with storage elements (flip-flops) on the same chip, enabling the implementation of sequential circuits such as counters, state machines, and registers.

General Architecture:

• Programmable AND-OR array: Implements the combinational next-state and output logic (as in a PAL/PLA).
• Flip-flops (usually D-type): Store the present state; their outputs are fed back into the AND array.
• Feedback paths: Route flip-flop outputs back to the inputs of the AND array to compute the next state.
• Output logic macrocells: Configurable blocks that allow the output to be registered (through the flip-flop) or combinational, with programmable polarity and feedback options.

Inputs --> [Programmable AND-OR Array] --> [D Flip-Flops] --> Outputs
^ |
|__ Feedback __|

Types:

• Registered PAL: PAL with output flip-flops.
• GAL (Generic Array Logic): Electrically erasable and reprogrammable, with configurable macrocells.

Advantage: A complete sequential circuit (state machine) can be implemented in a single reprogrammable chip.

Sequential PLDs integrate combinational logic and flip-flops, making them suitable for a wide range of sequential circuit applications:

• Finite State Machines (FSMs): Implement Mealy and Moore machines for control units in a single device.

• Counters: Binary, BCD, up/down, and modulo-N counters can be programmed easily.

• Shift Registers: Serial-in/serial-out, parallel data handling registers.

• Sequence Generators / Detectors: Generate specific bit sequences or detect patterns in serial data.

• Timing and Control Circuits: Generate control and timing signals in digital systems and microprocessor interfaces.

• Traffic Light Controllers, Vending Machine Controllers: Classic FSM-based control applications.

• Bus Interface and Handshaking Logic: Manage synchronization between subsystems.

Benefits:

• Reduced chip count, reprogrammability (in GAL-type devices), faster design cycles, and simplified board layout compared to using separate flip-flop and gate ICs.

A Field Programmable Gate Array (FPGA) is a high-density programmable logic device that can be configured by the user in the field to implement complex digital circuits. It offers far greater capacity and flexibility than PLAs or PALs.

Basic Architecture – Three main components:

• Configurable Logic Blocks (CLBs):

  • The basic building blocks arranged in a 2D array.
  • Each CLB contains Look-Up Tables (LUTs), flip-flops, and multiplexers to implement combinational and sequential logic.

• Programmable Interconnects (Routing):

  • A network of wires and programmable switches that connect CLBs to each other and to I/O blocks.

• Input/Output Blocks (IOBs):

  • Located along the periphery; interface the internal logic with external pins, with configurable direction and voltage standards.

[IOB][IOB][IOB][IOB]
[IOB][CLB][CLB][IOB]
[IOB][CLB][CLB][IOB]
[IOB][IOB][IOB][IOB]

Working:

• Logic functions are implemented using LUTs (small memories storing truth tables).
• Configuration data (bitstream) is loaded into SRAM cells, which program the LUTs, flip-flops, and interconnects.

Advantages: Reprogrammable, high logic capacity, supports parallel processing; used in DSP, communications, prototyping, and hardware acceleration.

A Look-Up Table (LUT) is the fundamental element used inside an FPGA's Configurable Logic Block to implement combinational logic.

Concept:

• An -input LUT is essentially a small memory (SRAM cells) with a multiplexer.
• The logic inputs act as the address/select lines to the multiplexer.
• The stored bit at the addressed location is the output of the function.

Implementing a Function:

• To implement any Boolean function of variables, the LUT is programmed by storing the truth table output in its memory cells.
• For each input combination (address), the corresponding truth-table value is fetched.

Example – 2-input LUT implementing :

• When , address = 01 selects the stored '1' → output 1.

Key Point:

• A single -input LUT can implement any function of those inputs simply by changing the stored contents.
• Typical FPGAs use 4-input to 6-input LUTs.

Applications:

• CPLD: Address decoding, bus interfacing, glue logic, simple state machines where instant-on and predictable timing matter.
• FPGA: Signal processing, image/video processing, communications, hardware acceleration, ASIC prototyping, and complex parallel systems.

Memory expansion combines multiple smaller memory chips to build a larger memory system.

1. Word Size (Bit) Expansion:

• Increases the number of bits per word while keeping the number of words the same.
• Chips are connected in parallel: same address and control lines to all chips, but data lines are grouped.

Example: To build a memory using two chips:

• Both chips share the same 4 address lines.
• Chip 1 provides data bits –, Chip 2 provides –.

2. Word Capacity Expansion:

• Increases the number of words while keeping the word size the same.
• Requires additional address lines and a decoder to select the appropriate chip via Chip Select (CS).

Example: To build a memory using two chips:

• 4 common address lines (–) go to both chips.
• One extra address line selects between chips through a 1-to-2 decoder driving the CS inputs.
  • → Chip 1 enabled (addresses 0–15)
  • → Chip 2 enabled (addresses 16–31)

Summary: Bit expansion widens the data bus; capacity expansion deepens the address space using chip-select decoding.

Notation Meaning:

• A memory specified as means it has words, and each word is 8 bits wide.

Number of Address Lines:

• The number of words is , where = number of address lines.
  
  

Number of Data Lines:

• Each word is 8 bits, so 8 data lines are required.
  

Total Storage Capacity:

Summary:

• Address lines = 12
• Data lines = 8
• Total capacity = 4 KB (32,768 bits)

General Formula:

• For a memory: address lines , data lines , total bits .

Volatile Memory:

• Loses its stored data when the power supply is switched off.
• Generally faster and used for temporary/working storage.

Non-Volatile Memory:

• Retains its stored data even without power.
• Used for permanent storage such as firmware, BIOS, and mass storage.

Classification:

Summary:

• Volatile: SRAM, DRAM — used as cache and main memory.
• Non-Volatile: ROM, EEPROM, Flash — used for permanent program/data storage.

Key Difference: Volatility determines whether the memory can serve as permanent storage (non-volatile) or only as temporary working memory (volatile).