Unit 4: Introduction to Sequential Logic Circuits - Subjective Questions

A sequential logic circuit is a type of digital circuit whose output depends not only on the present values of its inputs but also on the past history of inputs, i.e., its previous state. This memory capability is achieved through feedback paths and storage elements (latches/flip-flops).

Key differences:

• Memory:
  • Combinational: No memory; output depends only on current inputs.
  • Sequential: Has memory; output depends on current inputs and stored state.
• Feedback:
  • Combinational: No feedback path.
  • Sequential: Uses feedback from output to input.
• Clock:
  • Combinational: Not required.
  • Sequential: Often synchronized with a clock signal.
• Examples:
  • Combinational: Adders, multiplexers, decoders.
  • Sequential: Flip-flops, registers, counters.

Sequential circuits form the basis of memory elements, registers, and finite state machines in digital systems.

An SR-latch (Set-Reset latch) is the most basic bistable storage element built using two cross-coupled NOR gates.

Structure:

• Two NOR gates with outputs and fed back to the inputs of the other gate.
• Inputs: S (Set) and R (Reset).

Logic Diagram (NOR based):

Working:

• S=0, R=0 (Hold): Output retains its previous state (memory).
• S=1, R=0 (Set): Output , .
• S=0, R=1 (Reset): Output , .
• S=1, R=1 (Invalid): Both outputs go to 0, which violates complement rule. This is a forbidden state.

Truth Table:

The main drawback is the invalid state when both inputs are high.

An SR-latch using NAND gates is constructed by cross-coupling two NAND gates. It is also called an latch because it operates on active-LOW inputs.

Structure:

• Two cross-coupled NAND gates with inputs and .

Working (Active-LOW inputs):

Key Differences from NOR-based SR-latch:

• Active level:
  • NOR-based: Active-HIGH inputs (S=1, R=1 are active).
  • NAND-based: Active-LOW inputs (S=0, R=0 are active).
• Invalid condition:
  • NOR-based: Invalid when .
  • NAND-based: Invalid when .
• Hold condition:
  • NOR-based: Hold at .
  • NAND-based: Hold at .

The NAND latch is more commonly used in practice because NAND gates are cheaper and faster to fabricate.

A D-latch (Data or Transparent latch) is a modification of the gated SR-latch designed to eliminate the invalid/forbidden state.

Construction:

• A single data input D is connected to the S input.
• An inverter connects D to the R input, ensuring and are always complementary.
• An Enable (E) signal controls when the latch responds to D.

Operation:

• When E = 1 (enabled): Output follows the input, . The latch is transparent.
• When E = 0 (disabled): Output holds its previous value regardless of D.

Truth Table:

Advantages over SR-latch:

• No invalid state: Since S and R can never both be 1 (they are complements), the forbidden condition is eliminated.
• Simple data storage: Directly stores a single bit of data.
• Fewer control complications compared to managing two separate S and R inputs.

A D flip-flop (Data flip-flop) is an edge-triggered storage element that captures the value of the D input at a clock edge and holds it until the next active edge.

Logic Symbol:

• Inputs: D and Clock (CLK).
• Outputs: Q and .
• Triggered on the rising (↑) or falling (↓) edge of the clock.

Operation:

• At the active clock edge, the output takes the value of D: .
• Between clock edges, the output remains unchanged.

Characteristic Table:

Characteristic Equation:

Applications:

• Used in registers, data buffers, and shift registers.
• Introduces a delay of one clock cycle, hence sometimes called a Delay flip-flop.

The JK flip-flop is a refinement of the SR flip-flop that eliminates the invalid state by defining a useful toggle operation for the condition.

Inputs: J (analogous to Set) and K (analogous to Reset), plus clock.

Operation:

• J=0, K=0: No change (hold previous state).
• J=0, K=1: Reset, .
• J=1, K=0: Set, .
• J=1, K=1: Toggle — output complements its previous state.

Characteristic Table:

Characteristic Equation:

How it overcomes SR limitation:

• In an SR flip-flop, is forbidden (invalid).
• In the JK flip-flop, the equivalent condition produces a defined toggle action instead of an invalid state, making the flip-flop fully functional for all input combinations.

Note: Simple JK flip-flops suffer from the race-around condition when the clock pulse width is too large; this is solved using master-slave or edge-triggered designs.

The T flip-flop (Toggle flip-flop) is a single-input flip-flop obtained by connecting the J and K inputs of a JK flip-flop together (T = J = K).

Operation:

• T = 0: Output holds its previous state (no change).
• T = 1: Output toggles (complements) at each active clock edge.

Characteristic Table:

Characteristic Equation:

Main Application:

• Used extensively in the design of counters and frequency dividers. When T is held at 1, the output frequency becomes half of the input clock frequency, making it ideal for binary ripple counters.

Latches and flip-flops are both bistable storage devices but differ mainly in how they respond to control signals.

Summary: A latch is level-sensitive and transparent during its active enable period, whereas a flip-flop is edge-sensitive and captures data only at a specific clock transition, offering better synchronization in sequential circuits.

To convert an SR flip-flop to a D flip-flop, we express the S and R inputs in terms of the D input and present state .

Step 1 — Conversion Table:

(The S,R columns come from the SR flip-flop's excitation table.)

Step 2 — K-map Simplification:

For S (with don't-cares):

For R:

Step 3 — Logic Diagram:

• Connect input D directly to S.

• Connect D through an inverter to R (so ).

  D -------+--------> S
  |
  +--[NOT]--> R

This makes S and R always complementary, giving , which is exactly the D flip-flop behavior.

Part A: JK → T Flip-Flop

Conversion Table:

From the K-maps:

Logic connection: Simply tie J and K together and label the common input as T.

Part B: JK → D Flip-Flop

Conversion Table:

From the K-maps:

Logic connection: Connect D directly to J, and D through an inverter to K ().

These conversions rely on the excitation table of the JK flip-flop and K-map minimization.

To convert a D flip-flop into a JK flip-flop, we must express the D input in terms of J, K, and the present state .

Step 1 — Conversion Table:

Since for a D flip-flop , we have .

Step 2 — K-map for D (variables J, K, ):

Simplifying yields the JK characteristic equation:

Step 3 — Logic Diagram:

• Implement using AND, OR, and NOT gates.
• Feed this combinational logic into the D input of the flip-flop, with feedback from and .

This added combinational logic makes the D flip-flop behave like a JK flip-flop.

Race-around condition is an unstable behavior that occurs in a level-triggered JK flip-flop when both inputs are high ().

Cause:

• When and the clock is at level 1, the output toggles.
• If the propagation delay of the flip-flop is smaller than the clock pulse width, the output may toggle multiple times during the single high period of the clock.
• As a result, the final state at the end of the clock pulse becomes uncertain/unpredictable.

Condition for race-around:

where is propagation delay and is the clock pulse width.

Methods to eliminate it:

• 1. Reduce clock pulse width: Make so only one toggle can occur. This is impractical for very fast circuits.
• 2. Master-Slave configuration: Use two flip-flops (master and slave) so that the output changes only once per full clock cycle.
• 3. Edge triggering: Design the flip-flop to respond only to the rising or falling edge of the clock, giving an extremely narrow effective window that prevents multiple toggles.

Edge-triggered and master-slave flip-flops are the standard practical solutions.

A Master-Slave JK flip-flop consists of two clocked JK flip-flops connected in series — the master and the slave — with the clock applied directly to the master and its complement applied to the slave.

Block Diagram:

J --->| MASTER |---->| SLAVE |---> Q
K --->| JK FF | | JK FF |---> Q'
^ ^
CLK ----+----[NOT]----------+

Working:

• When CLK = 1 (high):
  • The master is enabled and responds to J and K inputs.
  • The slave is disabled (its clock is 0), so its output stays unchanged.
  • The master captures the new value.
• When CLK = 0 (low):
  • The master is disabled and holds its value.
  • The slave is enabled and copies the master's output to the final output Q.

Thus, the output changes only once per clock cycle, at the falling edge.

How it solves the race-around problem:

• Because the master and slave are never enabled simultaneously, the feedback loop is broken.
• Even with , the master can toggle only once during the high clock, and the slave transfers this single stable value during the low clock.
• This prevents the multiple-toggling (race-around) that afflicts a simple level-triggered JK flip-flop.

Note: Master-slave flip-flops may suffer from 1's catching / 0's catching, solved by edge-triggered designs.

Edge triggering is a technique in which a flip-flop changes its output state only at the transition (edge) of the clock signal, rather than during the entire high or low level. This provides precise timing control and prevents multiple output changes within one clock period.

Types of Edge Triggering:

1. Positive (Rising) Edge Triggering:

• The flip-flop responds when the clock transitions from 0 → 1 (LOW to HIGH).
• Denoted by a small triangle (>) on the clock input in the symbol.

2. Negative (Falling) Edge Triggering:

• The flip-flop responds when the clock transitions from 1 → 0 (HIGH to LOW).
• Denoted by a triangle with a bubble (○>) on the clock input.

Comparison:

Advantages of Edge Triggering:

• Eliminates race-around condition.
• Provides synchronous, predictable operation.
• Input is sampled only during the brief edge interval, reducing susceptibility to noise during the rest of the clock cycle.

The four basic flip-flops differ in their number of inputs and behavior. A comparison is given below.

Detailed Observations:

• SR flip-flop: Simplest, but has a forbidden state.
• D flip-flop: Single input, eliminates invalid state, ideal for data storage.
• JK flip-flop: Most versatile; toggles for , no invalid state.
• T flip-flop: Derived from JK; toggles for T=1, used in counters.

Summary: D and T are single-input flip-flops derived from the two-input SR and JK types. JK is considered the universal flip-flop since all others can be realized from it.

An excitation table specifies the required input(s) needed to cause a desired transition from the present state to the next state . It is the reverse of the characteristic table and is essential for designing sequential circuits.

1. SR Flip-Flop Excitation Table:

2. D Flip-Flop Excitation Table:

3. JK Flip-Flop Excitation Table:

4. T Flip-Flop Excitation Table:

Significance:

• Used to determine flip-flop input equations during counter and state machine design.
• The don't-care (X) entries provide flexibility, allowing simpler K-map simplifications and reduced logic.
• They are the foundation for flip-flop conversion and synchronous circuit synthesis.

A gated SR-latch (also called a clocked or enabled SR-latch) is a basic SR-latch with an additional Enable (E) or clock control signal that determines when the latch is allowed to respond to its S and R inputs.

Construction:

• Two AND (or NAND) gates are added at the S and R inputs.
• The enable signal is ANDed with both S and R before feeding the cross-coupled gates.

Operation:

• When E = 0: The gating gates block S and R; the latch holds its previous state regardless of input changes.
• When E = 1: The latch behaves like a normal SR-latch, responding to S and R.

Truth Table:

Why the clock/enable is added:

• Synchronization: Allows the latch to change state only at controlled times, enabling coordinated operation with other circuit elements.
• Noise immunity: Input changes are ignored when disabled, preventing accidental state changes.
• Foundation for flip-flops: Gated latches are the building blocks used to create edge-triggered flip-flops and master-slave configurations.

The 1's catching problem is an undesirable behavior that occurs in a master-slave JK flip-flop when unwanted spikes/glitches appear on the J or K inputs while the master flip-flop is enabled.

The Problem:

• During the time the clock is HIGH, the master is active and responsive to its inputs.
• If a momentary glitch (a brief 1) appears on the J input (even if it should have been 0), the master latch catches and stores that 1.
• This incorrect value is then transferred to the slave when the clock goes LOW.
• This is called 1's catching (a similar effect with the K input is called 0's catching).

Consequence:

• The flip-flop stores an incorrect value based on transient noise rather than the intended steady input, producing erroneous output.

How it is overcome:

• Edge-triggered flip-flops: Instead of being level-sensitive throughout the clock-high period, edge-triggered designs sample the inputs only during the brief clock transition (edge).
• Because the sampling window is extremely narrow, momentary glitches occurring elsewhere in the clock cycle are ignored.
• Thus, replacing the master-slave (level-sensitive) design with a true edge-triggered flip-flop eliminates the 1's/0's catching problem.

Modern flip-flops therefore use edge triggering for reliable, glitch-free operation.

A positive edge-triggered D flip-flop samples the D input only at the rising edge (0 → 1) of the clock and holds it until the next rising edge.

Rules for the timing diagram:

• The output Q changes only at the rising edge of CLK.
• At each rising edge, takes whatever value D has at that instant.
• Between rising edges, Q remains constant regardless of D.

Example Waveform Description:

CLK : |‾||‾||‾||‾|_
↑ ↑ ↑ ↑
D : |‾‾‾‾||‾‾‾‾‾‾

Q : __|‾‾‾‾‾‾||‾‾ (updates only at ↑ edges)

Explanation:

• 1st rising edge: Suppose D = 1 → Q becomes 1.
• 2nd rising edge: If D = 1 → Q stays 1.
• 3rd rising edge: If D = 0 → Q becomes 0.
• 4th rising edge: If D = 1 → Q becomes 1.

Key Points:

• Any change in D between clock edges has no effect on Q.
• Setup time (): D must be stable before the edge.
• Hold time (): D must remain stable for a short period after the edge.

This edge-triggered behavior ensures synchronous, predictable data capture, unlike a transparent latch which follows D whenever enabled.

Asynchronous inputs, namely Preset (PRE / ) and Clear (CLR / ), are additional control inputs on a flip-flop that can set or reset the output independently of the clock signal.

Definitions:

• Preset (PR): Forces the output to Q = 1 immediately, regardless of the clock, D, J, K inputs.
• Clear (CLR): Forces the output to Q = 0 immediately, regardless of the clock and other inputs.

These are usually active-LOW (denoted and ).

Operation (active-LOW example):

Purpose:

• Initialization: Set flip-flops/registers to a known starting state before normal operation (e.g., resetting a counter to 0).
• Immediate control: Override normal clocked operation for emergency reset or forced setting.
• System reset: Used in power-on reset circuits to bring the system to a defined state.

Note: Since they act independently of the clock, asynchronous inputs take priority over synchronous (clocked) inputs and must be used carefully to avoid unintended state changes.