Unit 5: Sequential Logic Circuits Applications

Sequential circuits differ from combinational logic because their outputs depend on both present inputs and stored past state, held in flip-flops clocked by a common signal. This unit builds registers and counters entirely from edge-triggered flip-flops (mostly D and JK) and treats them as the storage and timing backbone of digital systems.

• State element: the flip-flop, whose output changes only at a clock edge; n flip-flops give 2ⁿ possible states.
• Clocking discipline: synchronous devices share one clock so all flip-flops update simultaneously; asynchronous devices chain the clock, so change ripples through.
• Triggering: assume positive-edge triggering unless stated; the characteristic equations Q⁺ = D and Q⁺ = JQ' + K'Q govern next-state behaviour.
• Data movement conventions: serial means one bit per clock through a single line; parallel means all bits at once on separate lines.

II. Shift Registers — Serial Storage and Data Movement

A shift register is a cascade of flip-flops in which the output of one feeds the input of the next, so a stored bit pattern moves one position per clock pulse. Classification is by how data enters and leaves.

A. Operation of all basic Shift Registers

Each configuration is named by its input/output style (Serial/Parallel In, Serial/Parallel Out).

• SISO (Serial-In Serial-Out): data enters one bit per clock at the first D input and emerges n clocks later at the last output.
  • Example: a 4-bit SISO loaded with 1011 needs 4 clocks to fully shift in and 4 more to read out; it acts as a time-delay element of 4 clock periods.
• SIPO (Serial-In Parallel-Out): data shifts in serially, but every flip-flop output is tapped, so after n clocks the whole word is available in parallel — a serial-to-parallel converter.
• PISO (Parallel-In Serial-Out): all bits load simultaneously via a LOAD/SHIFT control gating the D inputs, then leave serially — a parallel-to-serial converter.
• PIPO (Parallel-In Parallel-Out): data loads and reads in parallel on one clock; it is simply a temporary storage register, no shifting used.

SISO stage:  Din → D0 Q0 → D1 Q1 → D2 Q2 → D3 Q3 → Dout
             (each Q feeds the next D; one shift per CLK edge)

Symbols: Din = serial input bit, Q0..Q3 = flip-flop outputs, CLK = common clock.

B. Significance and timing

• Data-rate matching: SIPO/PISO bridge serial links (UART, SPI) and parallel buses.
• Shift = arithmetic: a left shift multiplies a binary number by 2, a right shift divides by 2 (integer).
• Propagation limit: maximum clock frequency f_max ≤ 1/(t_pd + t_su), where t_pd is flip-flop delay and t_su is setup time.

III. Bidirectional Shift Register — Selectable Shift Direction

A bidirectional shift register can shift data either left or right under a direction-control input, unlike the fixed left-only or right-only basic types.

A. Bidirectional Shift Register

• Control line: a single M (mode) bit selects direction — M = 1 shifts right, M = 0 shifts left (convention may reverse).
• Steering logic: each flip-flop's D input is fed by a 2-to-1 multiplexer choosing between the right neighbour and the left neighbour.
  • Right shift path: D_i = Q_(i-1).
  • Left shift path: D_i = Q_(i+1).
• Serial inputs: two separate serial-in lines, one at each end, feed data during the respective direction.
• Use: implements reversible data movement and forms the core of arithmetic shift and rotate operations in ALUs.

Di = M · Q(i-1)  +  M' · Q(i+1)

Symbols: Di = D input of stage i, M = mode bit, Q(i-1)/Q(i+1) = neighbouring outputs.

IV. Universal Shift Register — All Modes in One Device

A universal shift register combines parallel load, both shift directions, and hold into a single device, selected by two mode bits — the most general register (e.g. the 74194).

A. Universal Shift Register

• Mode inputs: two select lines S1 S0 drive a 4-to-1 multiplexer at every flip-flop's D input.
  • 00 — Hold: D_i = Q_i, output frozen.
  • 01 — Shift right: D_i = Q_(i-1), right serial-in at MSB.
  • 10 — Shift left: D_i = Q_(i+1), left serial-in at LSB.
  • 11 — Parallel load: D_i = P_i, all bits loaded from parallel inputs.
• Building block: each stage = one flip-flop + one 4:1 MUX; a 4-bit unit needs four such stages.
• Role: a single programmable element replacing SISO, SIPO, PISO, PIPO and bidirectional registers, widely used in CPU register files and accumulators.

V. Counters — Design of Asynchronous and Synchronous Counters

A counter is a register that cycles through a fixed sequence of states, one transition per clock, using flip-flops wired so their combined outputs count clock pulses.

A. Design of Asynchronous counters

Also called ripple counters; here the clock drives only the first flip-flop and each subsequent flip-flop is clocked by the previous output.

• Ripple mechanism: flip-flops are configured in toggle mode (J = K = 1); Q0 toggles every clock, Q1 toggles when Q0 falls, and so on.
• MOD-2ⁿ counting: n toggle flip-flops give a natural binary count 0 → 2ⁿ − 1.
• Truncated (MOD-N) design: to stop short of 2ⁿ, decode the terminal state with a gate and asynchronously clear.
  • Example — MOD-10 (decade): four flip-flops count to 1010; a NAND on Q3 and Q1 resets all to 0000, giving states 0–9.
• Drawback: cumulative delay — total settling time = n × t_pd, so max frequency falls as bits increase, and transient false counts (glitches) can appear.

B. Design of Synchronous counters

All flip-flops receive the same clock edge simultaneously; the counting sequence is produced by combinational logic feeding each flip-flop's inputs.

• Design procedure (JK-based):
  1. Draw the state diagram and state table for the desired sequence.
  2. Use JK excitation table (0→0: J=0,K=X; 0→1: J=1,K=X; 1→0: J=X,K=1; 1→1: J=X,K=0) to find each input.
  3. K-map simplify each J and K as functions of present state.
  4. Realise the logic and connect the common clock.
• Result for a 3-bit up-counter:
  
  TEXT

    J0 = K0 = 1
    J1 = K1 = Q0
    J2 = K2 = Q0 · Q1

  
  Symbols: Q0 = LSB output, Q2 = MSB output; a flip-flop toggles only when all lower bits are 1.
• Advantage: no ripple delay — every output settles within one t_pd, so far faster and glitch-free; cost is extra combinational gates.

VI. Ring Counter and Johnson Ring Counter — Circulating Shift Registers

Both are shift registers with the last output fed back to the first input, so a data pattern circulates rather than a binary count being generated.

A. Ring counter

A ring counter feeds the final output straight back to the serial input, circulating a single pattern.

• Sequence: a single 1 is preset and rotates; for 4 bits: 1000 → 0100 → 0010 → 0001 → 1000.
• Modulus: n flip-flops give exactly n states (MOD-n), far fewer than 2ⁿ.
• Feature: each output is a naturally decoded, one-hot signal — no external decoder needed, ideal for sequencing and timing generation.
• Cost: poor flip-flop utilisation (only one bit active at a time).

B. Johnson ring counter

A Johnson (twisted-ring / switch-tail) counter feeds the complement of the last output back to the first input.

• Feedback: serial input = Q_last' instead of Q_last.
• Sequence: for 4 bits, states fill and empty: 0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000.
• Modulus: n flip-flops give 2n distinct states, double the ring counter for the same hardware.
• Decoding: each state is uniquely identified by a 2-input AND gate on adjacent outputs, giving 2n clean timing pulses.

C. Comparison

1. Ring counter: n states, one-hot output, zero decoding gates, but wastes half the possible patterns; needs correct single-1 preset.
2. Johnson counter: 2n states, doubles resolution from the same flip-flops, needs simple 2-input decoders and self-correction logic to escape illegal (unused) states.