1Which of the following best describes the structural organization of a Read-Only Memory (ROM)?
A.Programmable AND array and Programmable OR array
B.Fixed AND array (decoder) and Programmable OR array
C.Programmable AND array and Fixed OR array
D.Fixed AND array and Fixed OR array
Correct Answer: Fixed AND array (decoder) and Programmable OR array
Explanation:A ROM essentially consists of a decoder (which acts as a fixed AND array) that selects a word line, and a programmable OR array (the memory matrix) that outputs the stored data.
Incorrect! Try again.
2If a memory chip has 12 address lines and 8 data lines, what is its storage capacity in bits?
A. bits
B. bits
C. bits
D. bits
Correct Answer: bits
Explanation:The number of address lines () determines the number of words (), and the data lines () determine the bits per word. Capacity = bits.
Incorrect! Try again.
3Which type of memory uses a flip-flop (latch) as its basic storage element?
A.Dynamic RAM (DRAM)
B.Static RAM (SRAM)
C.EPROM
D.Mask ROM
Correct Answer: Static RAM (SRAM)
Explanation:SRAM uses bistable latching circuitry (flip-flops) to store each bit, meaning it retains data as long as power is supplied without needing refreshing.
Incorrect! Try again.
4Why does Dynamic RAM (DRAM) require periodic refreshing?
A.To clear the memory contents for new data
B.Because the charge stored on the internal capacitors leaks over time
C.To prevent the memory from overheating
D.To switch between Read and Write modes
Correct Answer: Because the charge stored on the internal capacitors leaks over time
Explanation:DRAM stores bits as charge on a parasitic capacitor. Since capacitors leak charge, the data must be read and rewritten (refreshed) periodically to prevent data loss.
Incorrect! Try again.
5In the context of Programmable Logic Devices (PLDs), what architecture does a PLA (Programmable Logic Array) differ from a PAL (Programmable Array Logic)?
A.PLA has a fixed AND array and a programmable OR array
B.PLA has a programmable AND array and a fixed OR array
C.PLA has both programmable AND and programmable OR arrays
D.PLA cannot implement sequential logic
Correct Answer: PLA has both programmable AND and programmable OR arrays
Explanation:A PLA offers the most flexibility in combinational logic design because both the AND plane (product terms) and the OR plane (sum terms) are programmable. A PAL has a programmable AND plane but a fixed OR plane.
Incorrect! Try again.
6Which of the following statements regarding SRAM vs. DRAM is true?
A.SRAM is slower and denser than DRAM
B.SRAM is faster but less dense (larger cell size) than DRAM
C.DRAM consumes more static power than SRAM
D.DRAM does not require refresh circuitry
Correct Answer: SRAM is faster but less dense (larger cell size) than DRAM
Explanation:SRAM is faster because it uses flip-flops (no refresh needed), but it takes more transistors per bit (typically 6), making it less dense and more expensive per bit than DRAM (1 transistor, 1 capacitor).
Incorrect! Try again.
7What is the primary method for erasing an EPROM (Erasable Programmable Read-Only Memory)?
A.Applying a high electrical voltage
B.Exposing the chip to Ultraviolet (UV) light
C.Rewriting the data directly
D.Turning off the power supply
Correct Answer: Exposing the chip to Ultraviolet (UV) light
Explanation:EPROMs have a quartz window on the package. Exposing the silicon die to strong UV light ionizes the insulating oxide regions, allowing the stored charge to dissipate, effectively erasing the chip.
Incorrect! Try again.
8Which memory type allows data to be erased and reprogrammed electrically, byte by byte?
A.Mask ROM
B.PROM
C.EPROM
D.EEPROM
Correct Answer: EEPROM
Explanation:Electrically Erasable Programmable Read-Only Memory (EEPROM) allows individual bytes to be erased and reprogrammed using electrical signals, unlike EPROM which is erased globally via UV light.
Incorrect! Try again.
9A PAL (Programmable Array Logic) device consists of:
A.A programmable AND array and a programmable OR array
B.A programmable AND array and a fixed OR array
C.A fixed AND array and a programmable OR array
D.A fixed AND array and a fixed OR array
Correct Answer: A programmable AND array and a fixed OR array
Explanation:The PAL architecture was developed to overcome the complexity and delay of PLAs. It uses a programmable AND array to generate product terms, which are connected to a fixed OR array.
Incorrect! Try again.
10In an FPGA, what does the acronym LUT stand for?
A.Logic User Table
B.Look-Up Table
C.Linear Unit Transistor
D.Latch Utility Type
Correct Answer: Look-Up Table
Explanation:A Look-Up Table (LUT) is a key component of an FPGA's logic block. It implements a truth table in a small SRAM block to define the boolean function of the logic cell.
Incorrect! Try again.
11Which device is generally considered the most suitable for prototyping complex digital systems due to its reconfigurability?
Explanation:FPGAs are field-programmable, meaning they can be configured and reconfigured by the user after manufacturing. This makes them ideal for prototyping and updating designs.
Incorrect! Try again.
12Sequential PLDs, such as the GAL (Generic Array Logic), typically include which component at the output of the combinational logic array?
A.A capacitor
B.A resistor network
C.A Macrocell (containing a Flip-Flop)
D.An ADC
Correct Answer: A Macrocell (containing a Flip-Flop)
Explanation:Sequential PLDs incorporate memory elements (flip-flops) within output blocks called Macrocells. This allows them to implement state machines and other sequential logic.
Incorrect! Try again.
13The total number of fuses in a PROM of size is:
A.
B.
C.
D.
Correct Answer:
Explanation:A PROM contains a fixed AND array (decoder) and a programmable OR array. The intersection of every decoder output (word line) and every data output line has a fuse. Therefore, there are words bits/word = fuses.
Incorrect! Try again.
14Which of the following is volatile memory?
A.Flash Memory
B.EEPROM
C.SRAM
D.PROM
Correct Answer: SRAM
Explanation:Volatile memory loses its data when power is removed. SRAM (and DRAM) are volatile. Flash, EEPROM, and PROM are non-volatile.
Incorrect! Try again.
15A combinational circuit is defined by the functions: and . How can this be implemented using a ROM?
A.Using a ROM
B.Using an ROM
C.Using an ROM
D.Using a ROM
Correct Answer: Using an ROM
Explanation:There are 3 input variables (), requiring address locations (word lines). There are 2 output functions (), requiring 2 data bits. Thus, an ROM is required.
Incorrect! Try again.
16What is the primary advantage of a PAL over a PLA?
A.PALs are more flexible.
B.PALs are slower.
C.PALs are easier to manufacture and faster due to the fixed OR array.
D.PALs have more fuses.
Correct Answer: PALs are easier to manufacture and faster due to the fixed OR array.
Explanation:Because the OR array is fixed (hardwired), signals travel faster through the device (less capacitance/resistance than programmable connections), and the manufacturing/programming complexity is reduced compared to a PLA.
Incorrect! Try again.
17In the context of CPLDs (Complex Programmable Logic Devices), what connects the multiple logic blocks (SPLDs) together?
A.A system bus
B.A Programmable Interconnect Matrix (PIM) / Global Interconnect
C.Direct hardwiring
D.External wires
Correct Answer: A Programmable Interconnect Matrix (PIM) / Global Interconnect
Explanation:A CPLD consists of multiple function blocks (similar to SPLDs) connected by a central global routing resource, often called a Programmable Interconnect Matrix, allowing signals to route between blocks.
Incorrect! Try again.
18Which of the following is characteristic of Flash Memory?
A.It is volatile.
B.It requires UV light to erase.
C.It uses a single transistor per cell and is block-erasable.
D.It is faster than SRAM.
Correct Answer: It uses a single transistor per cell and is block-erasable.
Explanation:Flash memory is a type of EEPROM that is high density (1 transistor/cell like floating-gate MOSFETs) and is erased in blocks rather than byte-by-byte, making it faster for bulk data storage.
Incorrect! Try again.
19The time required to valid data availability at the output after the address is applied to the memory is called:
A.Write time
B.Refresh time
C.Access time
D.Hold time
Correct Answer: Access time
Explanation:Access time is the time interval between the application of the address inputs and the appearance of valid data at the data outputs.
Incorrect! Try again.
20In a PLA, if a function requires 5 product terms but the device only supports 4 product terms per OR gate, the function:
A.Cannot be implemented
B.Must be simplified further or split across outputs if possible
C.Can be implemented by increasing voltage
D.Will automatically use an adjacent OR gate
Correct Answer: Must be simplified further or split across outputs if possible
Explanation:PLAs (and PALs) have physical limits on the number of product terms (inputs to the OR gate). If a function exceeds this, it must be minimized or decomposed to fit the hardware constraints.
Incorrect! Try again.
21Which programming technology is typically used in volatile FPGAs?
A.Antifuse
B.SRAM cells
C.Floating gate transistors
D.EPROM cells
Correct Answer: SRAM cells
Explanation:Most standard FPGAs use SRAM cells to store the configuration (LUT data and routing switches). This is why they must be configured (booted) from an external non-volatile source upon power-up.
Incorrect! Try again.
22How many address lines are required for a memory chip of capacity 16 KB (Kilobytes)?
23The Configurable Logic Block (CLB) is the fundamental building block of which device?
A.DRAM
B.PLA
C.FPGA
D.PAL
Correct Answer: FPGA
Explanation:FPGAs are composed of an array of Configurable Logic Blocks (CLBs) surrounded by programmable I/O blocks and connected via programmable interconnects.
Incorrect! Try again.
24Which of the following represents the correct hierarchy of logic density (low to high)?
A.SPLD < CPLD < FPGA
B.FPGA < CPLD < SPLD
C.CPLD < SPLD < FPGA
D.SPLD < FPGA < CPLD
Correct Answer: SPLD < CPLD < FPGA
Explanation:SPLDs (Simple PLDs like PAL/GAL) have low density. CPLDs integrate multiple SPLDs, offering medium density. FPGAs offer the highest density, capable of implementing entire processors.
Incorrect! Try again.
25What is the function of the Write Enable (WE) input in a RAM chip?
A.To enable the output buffers
B.To select the specific memory chip
C.To control whether data is written to or read from the memory
D.To refresh the data
Correct Answer: To control whether data is written to or read from the memory
Explanation:The WE input determines the operation mode. Generally, if WE is active (low usually), data on the input lines is written to the address. If inactive, a read operation occurs (assuming Chip Select is active).
Incorrect! Try again.
26A device that contains a fixed OR array and a programmable AND array is a:
A.ROM
B.PLA
C.PAL
D.RAM
Correct Answer: PAL
Explanation:This is the definition of a PAL (Programmable Array Logic). Note: ROM is fixed AND, programmable OR.
Incorrect! Try again.
27Which type of PLD is best described as an 'AND-OR-INVERT' structure where the user defines the AND connections?
A.PROM
B.PAL/PLA
C.SRAM
D.DRAM
Correct Answer: PAL/PLA
Explanation:Both PALs and PLAs implement Sum-of-Products logic, effectively creating an AND-OR structure. The 'Invert' capability is often available at the output macrocell.
Incorrect! Try again.
28In a PLA, the 'Program Table' lists:
A.The memory addresses
B.The product terms, inputs, and outputs
C.The refresh rate
D.The voltage levels
Correct Answer: The product terms, inputs, and outputs
Explanation:A PLA program table specifies which inputs are connected to the AND gates (product terms) and which product terms are connected to the OR gates (outputs).
Incorrect! Try again.
29For a memory system, 'Expansion of Word Length' is achieved by connecting memory chips in:
A.Series
B.Parallel (Address lines common, Data lines concatenated)
C.Cascade
D.Independent banks
Correct Answer: Parallel (Address lines common, Data lines concatenated)
Explanation:To increase word length (e.g., 4-bit to 8-bit), chips are connected in parallel. They share the same address lines and Chip Select, but their data lines are combined (D0-D3 from chip 1, D4-D7 from chip 2).
Incorrect! Try again.
30In a DRAM cell, the transistor acts as:
A.An amplifier
B.A switch
C.A resistor
D.A storage element
Correct Answer: A switch
Explanation:The transistor in a DRAM cell (1T-1C cell) acts as a switch (controlled by the word line) to connect the storage capacitor to the bit line for reading or writing.
Incorrect! Try again.
31Which of the following is an application of a PLA?
A.Large scale data storage like a Hard Drive
B.Implementing complex combinational logic with shared product terms
C.Main memory in a computer (RAM)
D.Dynamic image processing
Correct Answer: Implementing complex combinational logic with shared product terms
Explanation:PLAs are ideal for combinational logic functions, specifically those where multiple outputs share common product terms, which optimizes the hardware usage compared to a ROM.
Incorrect! Try again.
32What is a Registered PAL?
A.A PAL that is registered with the manufacturer
B.A PAL that includes flip-flops at the outputs for sequential logic
C.A PAL used only for combinational logic
D.A PAL with read-only capabilities
Correct Answer: A PAL that includes flip-flops at the outputs for sequential logic
Explanation:A registered PAL includes D flip-flops at the output of the OR gate array. This allows the device to store state information and implement sequential circuits like counters.
Incorrect! Try again.
33The process of programming a ROM by the manufacturer according to the customer's specification during the fabrication process creates a:
A.PROM
B.EPROM
C.Mask ROM
D.Flash Memory
Correct Answer: Mask ROM
Explanation:Mask ROM involves creating a customized mask for the metallization layer during silicon fabrication to hardwire the 1s and 0s. It is cost-effective only for very high volumes.
Incorrect! Try again.
34Compared to an ASIC, an FPGA has:
A.Higher unit cost and lower performance, but faster time-to-market
B.Lower unit cost and higher performance
C.No programmability
D.Fixed logic only
Correct Answer: Higher unit cost and lower performance, but faster time-to-market
Explanation:FPGAs have overhead due to the programmable routing and LUTs, making them slower and more expensive per unit than a custom ASIC. However, they don't require the expensive/slow fabrication setup (NRE costs), offering faster time-to-market.
Incorrect! Try again.
35What is the result of 'address decoding' in a memory unit?
A.Converting binary data to decimal
B.Selecting a specific memory word based on the address inputs
C.Refreshing the data
D.Calculating the parity bit
Correct Answer: Selecting a specific memory word based on the address inputs
Explanation:The address decoder takes the address bits and activates exactly one of the word lines, allowing access to that specific memory location.
Incorrect! Try again.
36In a memory, how many input lines and output lines are there respectively?
A.6 input, 4 output
B.64 input, 4 output
C.4 input, 64 output
D.6 input, 64 output
Correct Answer: 6 input, 4 output
Explanation:Capacity is , so 6 address input lines are needed. The word size is 4, so there are 4 data output lines.
Incorrect! Try again.
37Why are FPGAs considered 'Field Programmable'?
A.They can only be programmed in a magnetic field.
B.They can be programmed by the user 'in the field' (outside the factory).
C.They use Field Effect Transistors.
D.They are programmed using electric fields only.
Correct Answer: They can be programmed by the user 'in the field' (outside the factory).
Explanation:The term 'Field Programmable' indicates that the device's function is defined by the customer/designer after the device has left the manufacturing facility.
Incorrect! Try again.
38Which component in an FPGA allows for flexible connection between different CLBs?
Explanation:The programmable routing architecture (switch matrices) allows wires to be connected or disconnected to route signals between different Configurable Logic Blocks (CLBs).
Incorrect! Try again.
39In the implementation of combinational logic using a PLA, if two functions share a product term (e.g., ), how is this handled?
A.The term is generated twice in the AND plane.
B.The term is generated once in the AND plane and connected to both OR gates.
C.It cannot be handled; PLA does not support sharing.
D.External wiring is required.
Correct Answer: The term is generated once in the AND plane and connected to both OR gates.
Explanation:This is a key advantage of the PLA. The programmable OR array allows a single product term line from the AND array to be connected to multiple OR gates (outputs).
Incorrect! Try again.
40A typical Macrocell in a CPLD or SPLD consists of:
A.Combinational logic only
B.AND-OR array, a flip-flop, and a mux
C.Just a flip-flop
D.A DRAM cell
Correct Answer: AND-OR array, a flip-flop, and a mux
Explanation:A macrocell typically contains the logic sum (OR gate), a flip-flop for registration, and multiplexers to select between registered or combinatorial output, and polarity control.
Explanation:Antifuse FPGAs create permanent low-resistance paths when programmed. Once the antifuse is 'blown' (connected), it cannot be reversed. They are non-volatile.
Incorrect! Try again.
42If you need a memory to store the bootloader (BIOS) of a computer, which type is most appropriate?
A.SRAM
B.DRAM
C.ROM / Flash
D.Register
Correct Answer: ROM / Flash
Explanation:The BIOS code must be retained when the computer is turned off so it can boot up next time. Therefore, non-volatile memory like ROM or Flash is required.
Incorrect! Try again.
43The implementation of the function using a Decoder and an OR gate requires:
A.Connecting outputs 1, 2, 6, 7 of the decoder to the OR gate
B.Connecting outputs 0, 3, 4, 5 of the decoder to the OR gate
C.Using a decoder
D.Using NAND gates only
Correct Answer: Connecting outputs 1, 2, 6, 7 of the decoder to the OR gate
Explanation:A decoder generates minterms. To implement a function defined by a sum of minterms, you simply OR the decoder outputs corresponding to those minterms.
Incorrect! Try again.
44What is the main limitation of using a ROM to implement combinational logic?
A.It is volatile.
B.The size doubles for every additional input variable ().
C.It is slower than a PLA.
D.It cannot implement sequential logic.
Correct Answer: The size doubles for every additional input variable ().
Explanation:ROM requires a decoder that fully decodes all inputs. If you add 1 input variable, the number of words doubles. For many inputs with few used minterms, this is very inefficient compared to PLA/PAL.
Incorrect! Try again.
45Which PLD type is essentially a PROM?
A.Fixed AND, Programmable OR
B.Programmable AND, Fixed OR
C.Programmable AND, Programmable OR
D.Fixed AND, Fixed OR
Correct Answer: Fixed AND, Programmable OR
Explanation:A PROM architecture consists of a fixed address decoder (Fixed AND) and a programmable memory array (Programmable OR).
Incorrect! Try again.
46In an FPGA, the I/O Blocks (IOBs) are responsible for:
A.Storing logic functions
B.Routing signals internally
C.Interfacing internal logic with external pins
D.Generating the clock
Correct Answer: Interfacing internal logic with external pins
Explanation:I/O blocks provide the interface between the package pins and the internal logic, often handling voltage translation, buffering, and latching of signals.
Incorrect! Try again.
47What is the difference between a Static RAM cell and a Dynamic RAM cell in terms of component count?
Explanation:A standard CMOS SRAM cell uses 6 transistors (4 for the cross-coupled inverters, 2 access). A standard DRAM cell uses 1 transistor and 1 capacitor.
Incorrect! Try again.
48The speed of a memory is often measured by its:
A.Capacity
B.Word size
C.Bandwidth and Latency
D.Voltage
Correct Answer: Bandwidth and Latency
Explanation:Latency (Access time) is how long it takes to get data, and Bandwidth is how much data can be transferred per unit of time.
Incorrect! Try again.
49A logical function that has many 'don't care' conditions or unused minterms is most efficiently implemented in:
A.A ROM
B.A PLA
C.A Shift Register
D.A Counter
Correct Answer: A PLA
Explanation:A PLA only generates the specific product terms needed for the function. A ROM must have a physical storage cell for every possible input combination, effectively wasting space on 'don't cares' or unused minterms.
Incorrect! Try again.
50What is the role of the 'Chip Select' (CS) or 'Chip Enable' (CE) pin on a memory chip?
A.To provide power to the chip
B.To enable the chip to respond to control and address signals
C.To select the row in the matrix
D.To determine read or write mode
Correct Answer: To enable the chip to respond to control and address signals
Explanation:The CS/CE signal activates the I/O buffers and control logic of the specific chip. If CS is inactive, the chip ignores the bus and enters a low-power standby mode.