Unit3 - Subjective Questions

Full Adder Design:

A Full Adder is a combinational circuit that performs the addition of three bits: two significant bits ( and ) and a previous carry bit ().

1. Truth Table:

2. Boolean Expressions:
Using K-maps or direct observation:

• Sum ():
• Carry ():
  (Alternatively, )

3. Logic Implementation:

• Sum: Use two XOR gates.
• Carry: Use AND gates and an OR gate.

4:1 Multiplexer (MUX):

A 4:1 MUX has 4 data inputs (), 2 selection lines (), and 1 output (). It acts as a data selector.

1. Truth Table:

2. Boolean Expression:

3. Working:
Based on the binary value of the selection lines, one of the four inputs is connected to the output. For example, if , the term becomes High, selecting input to appear at .

Difference between Multiplexer (MUX) and Demultiplexer (DEMUX):

Half Subtractor Design:

A Half Subtractor computes the difference between two single bits ().

1. Truth Table:

2. Derivation:

• Difference (): High when inputs are different.
• Borrow (): High only when and .

3. Circuit:
Uses one XOR gate for Difference and one AND gate with an inverter on input A for Borrow.

CMOS Inverter:

CMOS (Complementary Metal-Oxide-Semiconductor) logic uses complementary pairs of p-type and n-type MOSFETs.

Structure:

• It consists of a PMOS transistor connected to (Pull-up network).
• It consists of an NMOS transistor connected to Ground (Pull-down network).
• The gates of both transistors are connected to the input (), and drains are connected to the output ().

Operation:

1. Input Low ($0$):
   • for NMOS is 0 NMOS is OFF (Open).
   • for PMOS is negative PMOS is ON (Closed).
   • Output is pulled up to (Logic High/1).
2. Input High ($1$):
   • for NMOS is positive NMOS is ON (Closed).
   • for PMOS is 0 PMOS is OFF (Open).
   • Output is pulled down to Ground (Logic Low/0).

Key Feature: Static power consumption is negligible because there is no direct path between and Ground in either steady state.

Logic Family Characteristics:

1. Fan-out:

• Fan-out is the maximum number of standard logic inputs (of the same logic family) that an output can drive reliably without degrading the voltage levels below the specified limits.
• High Fan-out is desirable.

2. Propagation Delay:

• It is the time delay between the application of an input signal and the change in the output signal.
• It is usually measured at the 50% voltage level of the transition. Shorter delay means faster speed.
• Average delay:

3. Noise Margin:

• It is the maximum noise voltage that can be added to an input signal without causing an undesirable change in the circuit output.
• It represents the circuit's immunity to noise. There is a High-state noise margin () and a Low-state noise margin ().

Implementing Boolean Function using 8:1 MUX:

Given function:
Variables: . We connect these to the select lines respectively.

Implementation Steps:

1. Select Lines: , , .
2. Data Inputs ( to ):
   • The input lines corresponding to the minterms present in the function (0, 2, 6, 7) are connected to Logic HIGH (1).
   • The input lines corresponding to minterms NOT present (1, 3, 4, 5) are connected to Logic LOW (0).

Connections:

The output of the MUX will generate the required function.

TTL NAND Gate with Totem Pole Output:

A standard TTL (Transistor-Transistor Logic) NAND gate typically uses a multi-emitter transistor at the input and a totem-pole arrangement at the output.

Circuit Structure:

1. Input Stage: A multi-emitter transistor (). Each emitter acts as an input. The base is connected to via a resistor.
2. Phase Splitter: Transistor . It drives the output transistors.
3. Output Stage (Totem Pole): Consists of a pull-up transistor (), a diode (), and a pull-down transistor ().

Operation:

• Case 1: Any Input is LOW (0):

  • The base-emitter junction of is forward-biased. Current flows out of the emitter.
  • The voltage at the base of drops, turning OFF.
  • Consequently, is OFF (Open).
  • is biased ON via the resistor connected to .
  • Output is pulled High (). Output = 1.

• Case 2: All Inputs are HIGH (1):

  • The base-emitter junction of is reverse-biased.
  • Current flows from through the base collector of into the base of , turning ON.
  • conducts, providing base current to , turning ON.
  • The voltage at the collector of drops, turning OFF.
  • Output is pulled Low () through . Output = 0.

3-to-8 Line Decoder:

A 3-to-8 decoder has 3 inputs () and 8 outputs ( to ). It activates one output corresponding to the binary value of the input.

1. Truth Table:

2. Logic Expressions:
Each output is a minterm of the inputs:

• ...

3. Logic Diagram:

• Use three NOT gates to generate complements of inputs.
• Use 8 AND gates (3-input each). Connect inputs to AND gates according to the boolean expressions above.

Magnitude Comparator:

A magnitude comparator is a combinational circuit that compares two numbers ( and ) and determines their relative magnitude. It has three outputs: , , and .

1-Bit Comparator:
Compares single bits and .

Logic Equations:

1. Equal (): High if both are 0 or both are 1. This is the XNOR function.
   
2. Greater (): High if and .
   
3. Lesser (): High if and .
   

Realizing Full Adder using Decoder:

A Full Adder has inputs and outputs Sum () and Carry (). A 3-to-8 decoder generates all minterms ( to ) for three variables.

1. Identify Minterms:

• Sum (): High for inputs 1, 2, 4, 7.
  
• Carry (): High for inputs 3, 5, 6, 7.
  

2. Implementation:

1. Connect inputs to the inputs of the 3-to-8 Decoder.
2. For Sum: Connect decoder outputs to a 4-input OR gate.
3. For Carry: Connect decoder outputs to another 4-input OR gate.

Comparison of Logic Families:

Parity Circuits:

Parity circuits are used for error detection in data transmission. A parity bit is added to the data to make the total number of 1s either Even (Even Parity) or Odd (Odd Parity).

• Parity Generator: A circuit at the transmitter that generates the parity bit based on the data message.
• Parity Checker: A circuit at the receiver that checks if the incoming data matches the expected parity rules.

3-bit Even Parity Generator:
For Even Parity, the total number of 1s (Data + Parity Bit) must be even.
Let data bits be and Parity bit be .

Logic:
If has an odd number of 1s, must be 1 (to make total even).
If has an even number of 1s, must be 0.
This behavior describes the XOR function.

Circuit:
Use two XOR gates. First compute , then XOR the result with .

Priority Encoder:

A standard encoder produces an error if more than one input is active simultaneously. A Priority Encoder solves this by assigning priority to the inputs.

Operation:

• If multiple inputs are active at the same time, the priority encoder generates the BCD code corresponding to the input with the highest priority.
• For example, in a 4-input priority encoder ( to ), if both and are high, and has higher priority, the output will represent 3 (Binary 11).

Example (Decimal to BCD Priority Encoder):
If input 9 is active, regardless of the status of inputs 0-8, the output is 1001 (BCD for 9). This ensures deterministic output in active environments like interrupt controllers.

Full Subtractor using Half Subtractors:

A Full Subtractor () produces Difference () and Borrow ().

Logic Expressions:

Implementation:

1. First Half Subtractor:
   • Inputs:
   • Outputs: ,
2. Second Half Subtractor:
   • Inputs: (from 1st HS),
   • Outputs: ,
3. OR Gate:
   • Combine the borrows from both stages.

This topology accurately implements the full subtractor logic.

Tri-state Logic:

Standard logic gates have two states: High (1) and Low (0). A Tri-state (or 3-state) device has a third state known as High Impedance (Hi-Z).

States:

1. Logic 0: Low voltage, sinks current.
2. Logic 1: High voltage, sources current.
3. High-Z: The output is effectively disconnected from the circuit (open circuit).

Control:
A control input (Enable) determines if the device operates normally or goes into Hi-Z.

Importance:

• Bus Sharing: In computer systems, multiple devices (CPU, Memory, I/O) share a common data bus. If normal gates were used, connecting outputs together would cause short circuits (one output trying to drive high, another low).
• Operation: Only one device is enabled at a time to drive the bus; all others are put in the Hi-Z state to prevent interference.

Open Collector Output:

In an Open Collector TTL gate, the top transistor () of the Totem Pole output stage is removed. The collector of the bottom pull-down transistor () is left open (unconnected internally).

Requirement for Pull-up Resistor:

• Because there is no internal path to for the output, the gate can only sink current (output Logic 0) but cannot source current (cannot output Logic 1) on its own.
• To provide the Logic 1 state, an external Pull-up Resistor connects the output to an external voltage supply ().
• When the transistor is OFF, the resistor pulls the line voltage up to High.

Applications:

• Wired-AND logic: Connecting multiple open-collector outputs together performs an AND operation.
• Driving loads: Driving lamps or relays requiring different voltage levels than the logic supply.

1-to-4 Demultiplexer (DEMUX):

Takes 1 Data Input () and directs it to one of 4 Outputs ( to ) based on 2 Select lines ().

Logic:

• If ,
• If ,
• If ,
• If ,

Logic Expressions:

Circuit:

• Two NOT gates for select lines.
• Four 3-input AND gates.
• Input goes to all AND gates. Select lines enable exactly one AND gate at a time.

BCD to 7-Segment Decoder:

This combinational circuit converts a 4-bit BCD input () into 7 outputs () to drive a 7-segment display.

Concept:

• Inputs: 0-9 in binary (0000 to 1001). Inputs 1010-1111 are 'Don't Cares' ().
• Outputs: Correlate to the segments required to display the decimal number.

Example Logic (Segment 'a'):
Segment 'a' is ON for digits: 0, 2, 3, 5, 6, 7, 8, 9.
Truth table Logic for 'a':

Using K-Map simplification, we derive the minimal expression for each of the 7 segments and implement them using AND, OR, and NOT gates.

NMOS NAND Gate:

Uses N-channel MOSFETs. It typically consists of a load transistor and driver transistors.

Structure:

1. Load Transistor: Usually a depletion-mode NMOS connected as a resistor (Gate connected to Source), or an enhancement mode NMOS with Gate to . It pulls the output High.
2. Driver Transistors: For a 2-input NAND gate, two enhancement-mode NMOS transistors are connected in Series between the Output node and Ground.

Operation:

• Output Low: Requires both driver transistors to conduct. This happens only if both Inputs AND are High (1). The series path pulls the output to Ground.
• Output High: If either A or B (or both) are Low (0), the path to ground is broken. The Load transistor pulls the output High ().

This behavior () confirms NAND operation.