Unit 3: Introduction to Combinational Logic Circuits

A combinational logic circuit is a system where the output depends only on the present values of the inputs. Unlike sequential circuits, combinational circuits do not have memory or feedback loops.

1. Arithmetic Circuits

Arithmetic circuits are essential components of the Arithmetic Logic Unit (ALU) in processors, handling binary addition and subtraction.

1.1 Adders

Half Adder

A combinational circuit that performs the addition of two single bits.

• Inputs: A, B
• Outputs: Sum (S), Carry (C)

Truth Table:

Boolean Expressions:

• (XOR operation)
• (AND operation)

Full Adder

A circuit capable of adding three bits: two significant bits and a carry bit from a previous stage.

• Inputs: A, B,
• Outputs: Sum (S),

Boolean Expressions:

• OR

Implementation: A Full Adder can be constructed using two Half Adders and one OR gate.

1.2 Subtractors

Half Subtractor

Performs subtraction of two single bits ().

• Inputs: A (Minuend), B (Subtrahend)
• Outputs: Difference (D), Borrow (B)

Boolean Expressions:

• (NOT-A AND B)

Full Subtractor

Performs subtraction involving three bits: Minuend, Subtrahend, and Borrow from the previous stage.

• Inputs: A, B,
• Outputs: Difference (D),

Boolean Expressions:

2. Comparators

A Digital Comparator compares the magnitude of two binary numbers (A and B) and generates three outputs based on the relationship between inputs.

1-Bit Comparator

• Outputs: , ,

Logic Expressions:

1. Equality (): (XNOR operation). High if inputs are identical.
2. Greater Than (): (A is 1, B is 0).
3. Less Than (): (A is 0, B is 1).

Magnitude Comparator (n-bit)

To compare multi-bit numbers, the circuit compares the Most Significant Bit (MSB) first. If MSBs are equal, it moves to the next lower bit. Commercial ICs like the 7485 allow cascading to compare 4-bit, 8-bit, or larger words.

3. Multiplexers and Demultiplexers

3.1 Multiplexer (MUX)

Often called a "Data Selector," a MUX directs one of several input lines to a single output line based on the selection lines.

• Relationship: Input lines require Selection lines.
• Structure: AND gates for selection, followed by a large OR gate for the output.

4-to-1 Multiplexer Example:

• Inputs:
• Select Lines:
• Output:

Output Expression:

Applications: Parallel-to-serial conversion, logic function implementation (universal logic circuit).

3.2 Demultiplexer (DEMUX)

Often called a "Data Distributor," a DEMUX takes a single input and routes it to one of several output lines.

• Relationship: 1 Input line, Selection lines, Output lines.
• Logic: Essentially a Decoder with an Enable input acting as the data line.

4. Decoders and Encoders

4.1 Decoders

A decoder converts binary information from input lines to a maximum of unique output lines. It detects the presence of a specific code.

3-to-8 Line Decoder:

• Inputs: x, y, z
• Outputs: through
• Operation: If input is 000, is active. If input is 111, is active.
• Active High vs. Low: Standard decoders usually have Active Low outputs (NAND gate based), meaning the selected output goes LOW (0), while all others stay HIGH (1).

4.2 Encoders

An encoder performs the inverse operation of a decoder. It converts an active input signal into a coded binary output.

• Inputs: (or fewer)
• Outputs: lines

Priority Encoder:
In standard encoders, if two inputs are active simultaneously, the output is undefined. A Priority Encoder solves this by assigning priority to inputs. If and are both active, the encoder outputs the binary code for (assuming higher index = higher priority).

5. Parity Circuits

Parity is the simplest method for error detection in data transmission.

Concepts

• Even Parity: The total number of 1s in the data (including the parity bit) must be even.
• Odd Parity: The total number of 1s in the data must be odd.

Parity Generator (Transmitter side)

A circuit that takes a data word and generates a parity bit to append to the message.

• Logic: Implemented using a cascade of XOR gates.
  • For 3-bit message (A, B, C) Even Parity: .

Parity Checker (Receiver side)

Checks the received data stream (Message + Parity Bit).

• If the parity is correct, the output is 0 (Error Free).
• If the parity is incorrect, the output is 1 (Error Detected).

6. Introduction to Logic Families

A "Logic Family" refers to a set of techniques used to implement logic within Very Large Scale Integration (VLSI) circuits. Families are categorized by the semiconductor components used (Bipolar vs. Unipolar).

Key Performance Parameters

1. Propagation Delay: The time difference between input application and output change. Lower is better.
2. Power Dissipation: Power consumed by the gate.
3. Fan-out: The maximum number of standard loads (inputs of other gates) an output can drive without signal degradation.
4. Noise Margin: The maximum noise voltage added to an input signal that does not cause a change in the output state.
5. Figure of Merit: Propagation Delay Power Dissipation.

Classification

• Bipolar Logic Families: Use Bipolar Junction Transistors (BJT). Examples: TTL, ECL.
• Unipolar Logic Families: Use Field Effect Transistors (FET). Examples: PMOS, NMOS, CMOS.

7. Structure and Operations of Logic Families

7.1 TTL (Transistor-Transistor Logic)

The most popular logic family for decades (e.g., 7400 series). It utilizes BJTs.

Structure (Standard TTL NAND Gate):

1. Multi-emitter Transistor: The input stage uses a transistor with multiple emitters (one for each logic input). This acts as an AND gate.
2. Phase Splitter: A transistor in the middle stage provides complementary signals to the output stage.
3. Totem-Pole Output: The output stage consists of two transistors stacked (one pull-up, one pull-down).
   • Operation: When Output is High, the upper transistor is ON, lower is OFF. When Output is Low, lower is ON, upper is OFF. This reduces power and increases speed compared to passive resistor loads.

Characteristics:

• Floating inputs are treated as Logic High.
• Fast switching speed.
• Moderate power consumption.

7.2 MOS Logic (NMOS / PMOS)

Uses Metal-Oxide-Semiconductor Field Effect Transistors.

• NMOS: Uses N-channel MOSFETs. Electrons are charge carriers. Faster than PMOS but historically slower than bipolar.
• Structure: Uses an enhancement-mode NMOS as the switch and a depletion-mode NMOS as the load resistor (active load).
• Advantages: High packing density (takes up less silicon space than BJT), low cost.

7.3 CMOS (Complementary MOS)

Currently the dominant technology in modern processors and memories.

Structure:
CMOS combines NMOS and PMOS transistors in complementary pairs.

• Inverter Example:
  • Top Transistor: PMOS (Source connected to ).
  • Bottom Transistor: NMOS (Source connected to Ground).
  • Gates: Connected together as Input.
  • Drains: Connected together as Output.

Operation:

1. Input = 0 (Low):
   • NMOS is OFF (Open).
   • PMOS is ON (Closed).
   • Output connects to (High).
2. Input = 1 (High):
   • NMOS is ON (Closed).
   • PMOS is OFF (Open).
   • Output connects to Ground (Low).

Key Advantage - Power:
In CMOS, the NMOS and PMOS are never ON simultaneously during a steady state. Therefore, there is almost zero static power dissipation. Power is only consumed during switching (dynamic power).

Comparison Summary: