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Unit 5: Adder Chronicles - Practice Quiz

ECE120 — Basic Electronics Engineering Workshop 60 Questions
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1 How many input bits are used in a half adder?

Design of a half adder Easy
A. Two input bits
B. One input bit
C. Three input bits
D. Four input bits

2 What are the two outputs of a half adder?

Design of a half adder Easy
A. Input and output
B. Clock and reset
C. Enable and select
D. Sum and carry

3 Which logic gate produces the Sum output of a half adder?

Design of a half adder Easy
A. AND gate
B. OR gate
C. NOT gate
D. XOR gate

4 Which logic gate produces the Carry output of a half adder?

Design of a half adder Easy
A. XOR gate
B. OR gate
C. NOT gate
D. AND gate

5 What is the Sum output of a half adder when and ?

Design of a half adder Easy
A. 2
B. Undefined
C. 0
D. 1

6 What is the Carry output of a half adder when and ?

Design of a half adder Easy
A. 0
B. Undefined
C. 2
D. 1

7 Which operation does a half adder perform?

Design of a half adder Easy
A. Decimal multiplication
B. Binary subtraction
C. Single-bit addition
D. Bit comparison

8 How many input bits are used in a full adder?

Design of a full adder Easy
A. Three input bits
B. Two input bits
C. One input bit
D. Four input bits

9 What is the additional input of a full adder compared with a half adder?

Design of a full adder Easy
A. Output sum
B. Input carry
C. Clock signal
D. Output carry

10 What are the outputs of a full adder?

Design of a full adder Easy
A. Input and carry
B. Sum and carry
C. Clock and sum
D. Select and enable

11 Which expression represents the Sum output of a full adder?

Design of a full adder Easy
A.
B.
C.
D.

12 What is the Sum output of a full adder when , , and ?

Design of a full adder Easy
A. 2
B. Undefined
C. 0
D. 1

13 What is the Carry output of a full adder when , , and ?

Design of a full adder Easy
A. 0
B. 2
C. Undefined
D. 1

14 A full adder can be constructed using how many half adders and one OR gate?

Design of a full adder Easy
A. Two half adders
B. Three half adders
C. Four half adders
D. One half adder

15 What does represent in a full adder?

Design of a full adder Easy
A. Input carry
B. Output carry
C. Output control
D. Input clock

16 Which tool is commonly used to list all input and output combinations of a logic circuit?

Validation of combinational logic Easy
A. Connection chart
B. Truth table
C. Timing clock
D. Power table

17 What should be compared when validating a combinational logic circuit?

Validation of combinational logic Easy
A. Gate sizes and labels
B. Expected and observed outputs
C. Input and wire colors
D. Power and ground lengths

18 How many input combinations are possible for a circuit with three binary inputs?

Validation of combinational logic Easy
A. Nine combinations
B. Six combinations
C. Three combinations
D. Eight combinations

19 What is a combinational logic circuit's output based on?

Validation of combinational logic Easy
A. Clock frequency values
B. Stored memory values
C. Previous output values
D. Present input values

20 Which method can be used to validate an adder circuit in a workshop?

Validation of combinational logic Easy
A. Testing input combinations
B. Changing the circuit color
C. Removing all input signals
D. Measuring wire length

21 A half adder receives inputs and . What are its sum and carry outputs?

Design of a half adder Medium
A. Sum = 1, Carry = 0
B. Sum = 1, Carry = 1
C. Sum = 0, Carry = 0
D. Sum = 0, Carry = 1

22 Which combination of logic gates correctly implements a half adder?

Design of a half adder Medium
A. OR gate for sum and AND gate for carry
B. NOR gate for sum and XOR gate for carry
C. AND gate for sum and XOR gate for carry
D. XOR gate for sum and AND gate for carry

23 A half adder has a sum output of and a carry output of . Which input condition must be present?

Design of a half adder Medium
A.
B.
C. Both B and C are possible
D.

24 If the AND gate in a half-adder circuit is replaced by an OR gate while the XOR gate remains unchanged, which output behavior is affected?

Design of a half adder Medium
A. Only the sum output is affected
B. Both outputs become complements
C. Both outputs remain unchanged
D. Only the carry output is affected

25 Which input combination produces a carry but no sum in a half adder?

Design of a half adder Medium
A.
B.
C.
D.

26 A half adder is used to add two single-bit numbers. For inputs and , what binary value is represented by the combined carry and sum outputs?

Design of a half adder Medium
A.
B.
C.
D.

27 A designer wants to implement the half-adder sum using only basic AND, OR, and NOT gates. Which Boolean expression should be used?

Design of a half adder Medium
A.
B.
C.
D.

28 A full adder receives , , and carry-in . What are the sum and carry-out?

Design of a full adder Medium
A. Sum = 0, Carry-out = 0
B. Sum = 0, Carry-out = 1
C. Sum = 1, Carry-out = 1
D. Sum = 1, Carry-out = 0

29 Which Boolean expression represents the sum output of a full adder?

Design of a full adder Medium
A.
B.
C.
D.

30 Which expression correctly represents the carry-out of a full adder?

Design of a full adder Medium
A.
B.
C.
D.

31 How can a full adder be constructed using half adders and an OR gate?

Design of a full adder Medium
A. Two half adders and one AND gate
B. Three half adders and one XOR gate
C. One half adder and one OR gate
D. Two half adders and one OR gate

32 For a full adder, the sum output is and the carry-out is . Which input condition is possible?

Design of a full adder Medium
A.
B.
C.
D.

33 A full adder has inputs , , and . What is the decimal value represented by its outputs?

Design of a full adder Medium
A. Two
B. One
C. Zero
D. Three

34 A full-adder circuit is designed with two XOR gates, two AND gates, and one OR gate. Which signal is normally connected to the second XOR gate along with the first XOR output?

Design of a full adder Medium
A. Carry-in
B. Input
C. Carry-out
D. Input

35 What is the most appropriate method for validating a newly built full-adder circuit?

Validation of combinational logic Medium
A. Compare measured outputs with the complete truth table
B. Test only the all-zero input
C. Measure only the supply voltage
D. Check the circuit only when the sum is one

36 During testing of a half adder, the carry output is always , including for and . Which fault is most likely?

Validation of combinational logic Medium
A. The output indicator is connected to ground
B. The supply frequency is too high
C. The AND gate or its wiring is faulty
D. The XOR input is shorted

37 A full-adder test gives the correct sum for all input combinations but an incorrect carry-out. Which part should be checked first?

Validation of combinational logic Medium
A. The XOR network for the sum
B. The carry-generation network
C. The circuit's clock source
D. The input switches for only

38 When validating combinational logic on a breadboard, why should unused logic inputs not be left floating?

Validation of combinational logic Medium
A. Floating inputs can produce unpredictable logic levels
B. Floating inputs permanently damage every logic gate
C. Floating inputs increase the circuit's clock speed
D. Floating inputs always force the output to zero

39 A measured full-adder output disagrees with the truth table only when , , and . What output should be expected for this test?

Validation of combinational logic Medium
A. Sum = 0, Carry-out = 0
B. Sum = 1, Carry-out = 1
C. Sum = 0, Carry-out = 1
D. Sum = 1, Carry-out = 0

40 A logic probe shows an undefined reading at the sum output while testing a half adder. Which action is most suitable before concluding that the design is incorrect?

Validation of combinational logic Medium
A. Tie the sum output directly to supply
B. Verify power, ground, and input connections
C. Replace the XOR gate with a NOT gate
D. Ignore the reading and test only carry

41 A half adder is implemented using only NAND gates. Which minimized two-output realization correctly produces sum and carry for inputs and ?

Design of a half adder Hard
A. ,
B. ,
C. ,
D. ,

42 A half adder uses active-high inputs and outputs. Its sum output is accidentally connected to an AND gate while its carry output is connected to an XOR gate. Which input condition exposes both wiring errors simultaneously?

Design of a half adder Hard
A. ,
B. ,
C. ,
D. ,

43 A half-adder sum is specified as , but the available gates are one 2-input OR gate and one 2-input AND gate. An inverter is also available. Which expression implements the sum with the fewest additional gates?

Design of a half adder Hard
A.
B.
C.
D.

44 A half adder is described by the canonical sum-of-products expression for its carry output. Which expression is correct, and why is no minterm required for the sum output at input ?

Design of a half adder Hard
A. ; the sum is one when both inputs are one
B. ; the sum is zero when both inputs are equal
C. ; the sum is zero when both inputs are one
D. ; the sum is one whenever is one

45 Two half adders are cascaded incorrectly by feeding the first half-adder carry into the second half-adder along with an external bit . For , , and , what are the final sum and carry outputs of this cascade?

Design of a half adder Hard
A. ,
B. ,
C. ,
D. ,

46 A half-adder circuit uses positive-logic XOR and AND gates, but its inputs are active-low signals and . Which output equations represent active-high versions of the arithmetic sum and carry?

Design of a half adder Hard
A. ,
B. ,
C. ,
D. ,

47 A half-adder implementation has propagation delays of through its XOR path and through its AND path. If both inputs change simultaneously from to , which transient behavior is expected under an inertial-delay model?

Design of a half adder Hard
A. The sum pulses high before returning low, while carry rises
B. The sum rises after and the carry remains low
C. The sum and carry rise together after the XOR delay
D. The sum remains low and the carry rises after

48 Which Boolean expression gives the carry output of a full adder in terms of augend , addend , and carry-in ?

Design of a full adder Hard
A.
B.
C.
D.

49 A full adder is constructed from two half adders and an OR gate. If the first half adder produces from and the second produces from , which carry equation results?

Design of a full adder Hard
A.
B.
C.
D.

50 For a full adder with inputs , , and , which output pair is correct and what arithmetic condition does it represent?

Design of a full adder Hard
A. , ; the total is binary
B. , ; the total is binary
C. , ; the total is binary
D. , ; the total is binary

51 A full-adder sum output is implemented as . If the first XOR gate has a stuck-at-zero output, for which input set is the observed sum incorrect?

Design of a full adder Hard
A. , ,
B. , ,
C. , ,
D. , ,

52 A ripple-carry adder is formed from four full adders. The carry propagation delay of each stage is , and the final sum logic settles after its carry-in settles. What is the worst-case delay from a carry-in change at the least significant stage to the most significant sum output?

Design of a full adder Hard
A.
B.
C.
D.

53 A full adder must be designed using only 2-input XOR, AND, and OR gates. Which gate-count combination implements both outputs with no shared intermediate node?

Design of a full adder Hard
A. Two XOR, two AND, one OR
B. One XOR, two AND, two OR
C. Three XOR, two AND, two OR
D. Two XOR, three AND, one OR

54 For a full adder, the carry output is required to be independent of for a particular pair . Which pair satisfies this condition, and what is the resulting carry value?

Design of a full adder Hard
A. ; for either carry-in
B. ; for either carry-in
C. ; for either carry-in
D. ; for either carry-in

55 A full adder is used to add three one-bit operands. If the sum output is correct but the carry output is replaced by , which input combination produces an incorrect carry?

Design of a full adder Hard
A. , ,
B. , ,
C. , ,
D. , ,

56 A combinational circuit has three inputs, and its output is one for minterms . Which input sequence provides complete functional validation when all possible static input combinations are tested?

Validation of combinational logic Hard
A.
B.
C.
D.

57 A measured full-adder truth table shows the correct outputs for all cases except , , , where the measured result is , . Which fault best explains this isolated error?

Validation of combinational logic Hard
A. The carry term is missing
B. The input is permanently held at one
C. The carry output is stuck at zero
D. The sum XOR network is stuck at zero

58 During validation of a two-level combinational circuit, the output briefly pulses when input changes from to while . The steady-state function is . Which explanation is most appropriate?

Validation of combinational logic Hard
A. The circuit has a static-1 hazard caused by unequal path delays
B. The truth table is invalid because OR gates cannot produce pulses
C. The circuit is sequential because the output depends on prior inputs
D. The circuit has a static-0 hazard because both inputs are zero

59 A logic analyzer samples a full-adder output at the exact instant inputs change. Why can this method falsely suggest an incorrect truth-table entry?

Validation of combinational logic Hard
A. Truth tables apply only when inputs change asynchronously
B. Combinational outputs may be transient before propagation settles
C. Logic analyzers automatically invert carry outputs
D. Full adders retain the previous output until reset

60 A half-adder testbench checks only input pairs and and observes correct outputs. Which conclusion is justified?

Validation of combinational logic Hard
A. The carry function is validated, but the sum function is not fully validated
B. Both functions are fully validated because equal inputs were tested
C. Neither function is validated because unequal inputs were omitted
D. The sum function is validated, but the carry function is not validated
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