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Unit 4: Universal Gate Adventure - Practice Quiz

ECE120 — Basic Electronics Engineering Workshop 60 Questions
0 Correct 0 Wrong 60 Left
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1 What is the main purpose of using a truth table while validating a logic gate?

Implementation and validation of logic gates Easy
A. To calculate the power supply frequency
B. To compare expected and observed outputs
C. To identify the color of connecting wires
D. To measure the physical size of the gate

2 How many possible input combinations must be tested for a two-input logic gate?

Implementation and validation of logic gates Easy
A. Three combinations
B. Eight combinations
C. Two combinations
D. Four combinations

3 For a two-input AND gate, which input combination produces a HIGH output?

Implementation and validation of logic gates Easy
A. ,
B. ,
C. ,
D. ,

4 For a two-input OR gate, which input combination produces a LOW output?

Implementation and validation of logic gates Easy
A. ,
B. ,
C. ,
D. ,

5 If the input of a NOT gate is HIGH, what should its output be during validation?

Implementation and validation of logic gates Easy
A. Floating
B. HIGH
C. LOW
D. Unchanged

6 When does a two-input NAND gate produce a LOW output?

Implementation and validation of logic gates Easy
A. When both inputs are HIGH
B. When both inputs are LOW
C. When the inputs are different
D. When either input is LOW

7 When does a two-input NOR gate produce a HIGH output?

Implementation and validation of logic gates Easy
A. When either input is HIGH
B. When both inputs are LOW
C. When the inputs are different
D. When both inputs are HIGH

8 What is the output of a two-input XOR gate when its inputs are different?

Implementation and validation of logic gates Easy
A. Always floating
B. Always LOW
C. Always HIGH
D. Always unchanged

9 Which instrument can be used to check whether a digital signal is HIGH or LOW?

Implementation and validation of logic gates Easy
A. Solder sucker
B. Logic probe
C. Screwdriver
D. Wire stripper

10 Why should unused logic-gate inputs not be left floating during validation?

Implementation and validation of logic gates Easy
A. They may change the gate symbol
B. They may reduce the input count
C. They may increase the wire length
D. They may cause unpredictable outputs

11 Which pair consists entirely of universal logic gates?

Design of logic gates using universal gates Easy
A. AND and OR
B. NAND and NOR
C. NOT and XOR
D. OR and XOR

12 How can a two-input NAND gate be used as a NOT gate for input ?

Design of logic gates using universal gates Easy
A. Connect to both inputs
B. Connect one input to ground
C. Leave both inputs unconnected
D. Connect the output to ground

13 Which arrangement implements an AND gate using only NAND gates?

Design of logic gates using universal gates Easy
A. One NAND gate followed by a NOR inverter
B. One NAND gate followed by a NAND inverter
C. One NOR gate followed by a NAND inverter
D. One OR gate followed by a NOR inverter

14 To implement an OR gate using NAND gates, what is done before applying the inputs to the final NAND gate?

Design of logic gates using universal gates Easy
A. Both inputs are grounded
B. Both inputs are disconnected
C. Both inputs are added
D. Both inputs are inverted

15 How can a two-input NOR gate be used as a NOT gate for input ?

Design of logic gates using universal gates Easy
A. Connect to both inputs
B. Connect the output to HIGH
C. Leave both inputs floating
D. Connect one input to HIGH

16 Which arrangement implements an OR gate using only NOR gates?

Design of logic gates using universal gates Easy
A. One NOR gate followed by a NAND inverter
B. One NOR gate followed by a NOR inverter
C. One AND gate followed by a NAND inverter
D. One NAND gate followed by a NOR inverter

17 To implement an AND gate using NOR gates, what is done to inputs and before the final NOR operation?

Design of logic gates using universal gates Easy
A. Both inputs are inverted
B. Both inputs are grounded
C. Both inputs are shorted
D. Both inputs are removed

18 Which expression represents an OR gate implemented with NAND operations?

Design of logic gates using universal gates Easy
A.
B.
C.
D.

19 What does the term "universal gate" mean?

Design of logic gates using universal gates Easy
A. A gate that operates without a power supply
B. A gate that always produces a HIGH output
C. A gate that accepts only one input signal
D. A gate that can build any Boolean function

20 What is the minimum number of two-input NAND gates needed to implement a NOT gate?

Design of logic gates using universal gates Easy
A. One gate
B. Two gates
C. Three gates
D. Four gates

21 During the validation of a two-input XOR gate, which output sequence should be observed for inputs ?

Implementation and validation of logic gates Medium
A.
B.
C.
D.

22 A two-input NAND gate produces HIGH for every tested input combination, including . Which fault best explains this result?

Implementation and validation of logic gates Medium
A. Both inputs are shorted together
B. The output is stuck HIGH
C. The gate behaves as an XOR gate
D. The output is stuck LOW

23 An AND gate is tested with inputs and , but its output is measured as HIGH. What should the expected output be?

Implementation and validation of logic gates Medium
A. HIGH, because the inputs are different
B. LOW, because both inputs are not HIGH
C. HIGH, because one input is HIGH
D. LOW, because both inputs are not LOW

24 A logic circuit gives the output sequence for inputs . Which gate has been implemented?

Implementation and validation of logic gates Medium
A. XNOR gate
B. XOR gate
C. NOR gate
D. NAND gate

25 While validating a NOT gate, the input is changed from LOW to HIGH. What output transition confirms correct operation?

Implementation and validation of logic gates Medium
A. HIGH to HIGH
B. LOW to HIGH
C. HIGH to LOW
D. LOW to LOW

26 Two switches provide the inputs to an OR gate. An LED connected to the output should turn on under which condition?

Implementation and validation of logic gates Medium
A. Exactly one switch is OFF
B. At least one switch is ON
C. Both switches are OFF
D. Both switches have equal states

27 A two-input NOR gate is operating correctly. For which input combination should its output LED turn on?

Implementation and validation of logic gates Medium
A.
B.
C.
D.

28 A circuit intended to implement produces LOW only for . What does this observation indicate?

Implementation and validation of logic gates Medium
A. The XOR gate is functioning correctly
B. The AND gate is functioning correctly
C. The NAND gate is functioning correctly
D. The OR gate is functioning correctly

29 When checking a logic-gate truth table experimentally, why should every possible input combination be applied?

Implementation and validation of logic gates Medium
A. To determine the package pin count
B. To increase the output voltage level
C. To verify the complete logical behavior
D. To reduce the circuit propagation delay

30 An XOR gate has inputs and . If is permanently connected to logic HIGH, how does the output depend on ?

Implementation and validation of logic gates Medium
A. The output is
B. The output is always LOW
C. The output is always HIGH
D. The output is equal to

31 How can a two-input NAND gate be connected to function as a NOT gate?

Design of logic gates using universal gates Medium
A. Connect one input permanently to LOW
B. Connect both inputs to the same signal
C. Connect the two inputs to complementary signals
D. Connect the output back to one input

32 What is the minimum number of two-input NAND gates required to implement a two-input AND gate?

Design of logic gates using universal gates Medium
A. Two NAND gates
B. Three NAND gates
C. One NAND gate
D. Four NAND gates

33 Which NAND-only arrangement implements the OR function ?

Design of logic gates using universal gates Medium
A. NAND both inputs, then invert the result
B. Invert one input, then NAND both inputs
C. NAND both inputs through a single gate
D. Invert both inputs, then NAND them

34 How can a NOR gate be used as an inverter?

Design of logic gates using universal gates Medium
A. Connect the output to both inputs
B. Apply complementary signals to the inputs
C. Connect one input permanently to HIGH
D. Connect both inputs to the same signal

35 What is the minimum number of two-input NOR gates required to implement a two-input OR gate?

Design of logic gates using universal gates Medium
A. Four NOR gates
B. Three NOR gates
C. One NOR gate
D. Two NOR gates

36 The outputs of two NOR gates are and . If and are applied to another NOR gate, what is the final expression?

Design of logic gates using universal gates Medium
A.
B.
C.
D.

37 A NAND-only circuit first generates and then applies and to a NAND gate. Which function is produced?

Design of logic gates using universal gates Medium
A.
B.
C.
D.

38 A standard two-input XOR circuit is constructed using only two-input NAND gates. How many NAND gates are required?

Design of logic gates using universal gates Medium
A. Two NAND gates
B. Four NAND gates
C. Three NAND gates
D. Five NAND gates

39 A designer must implement using only NAND gates. Which simplification is most useful?

Design of logic gates using universal gates Medium
A.
B.
C.
D.

40 Why are NAND and NOR gates described as universal gates?

Design of logic gates using universal gates Medium
A. Both types produce identical truth tables
B. Either type can implement any Boolean function
C. Both types always use only two inputs
D. Either type eliminates propagation delay

41 A NAND-gate implementation is tested with inputs and . The measured output remains at logic 1 for approximately before changing to logic 0. Which conclusion is most appropriate?

Implementation and validation of logic gates Hard
A. The circuit has an invalid truth table
B. The circuit is permanently stuck at logic 1
C. The circuit has a propagation delay of
D. The circuit implements an XOR gate

42 Using only 2-input NAND gates, which expression correctly implements the function ?

Design of logic gates using universal gates Hard
A.
B.
C.
D.

43 A NOR-based circuit is intended to implement . During validation, the output is measured as logic 1 for and logic 0 for all other input combinations. What is the best diagnosis?

Implementation and validation of logic gates Hard
A. The input terminals are electrically shorted
B. The circuit is behaving as an AND gate
C. The measured behavior matches a NOR gate
D. The output should be logic 1 for only

44 What is the minimum number of 2-input NAND gates required to implement without using any other gate type?

Design of logic gates using universal gates Hard
A. Three
B. Five
C. Four
D. Six

45 A 3-input NAND gate is validated by connecting its unused input permanently to logic 1 while applying signals to the other two inputs. Which 2-input function is observed at the output?

Implementation and validation of logic gates Hard
A.
B.
C.
D.

46 A NOR-only design must implement . Which expression is correct?

Design of logic gates using universal gates Hard
A.
B.
C.
D.

47 Two cascaded inverters are used to validate logic-level restoration. The first inverter has and ; the second has and . What is the maximum rise-or-fall propagation delay through the chain?

Implementation and validation of logic gates Hard
A.
B.
C.
D.

48 Using NAND gates, which implementation realizes a 2:1 multiplexer with select input , data inputs , and output ?

Design of logic gates using universal gates Hard
A.
B.
C.
D.

49 A NAND gate output is connected to an LED through a resistor to ground. The LED turns on when the output is high. Which input sequence tests all logically distinct output transitions most efficiently?

Implementation and validation of logic gates Hard
A.
B.
C.
D.

50 A NAND-only implementation of is required using only 2-input NAND gates. What is the minimum number of gates?

Design of logic gates using universal gates Hard
A. Six
B. Four
C. Five
D. Seven

51 A CMOS NAND input is accidentally left floating during validation. The observed output changes when a nearby jumper wire is moved. Which explanation is most accurate?

Implementation and validation of logic gates Hard
A. The floating input picks up noise and has an undefined logic level
B. The NAND gate automatically converts the floating input to logic 0
C. The output is guaranteed to remain high because CMOS inputs are ideal
D. The nearby wire changes the Boolean expression of the NAND gate

52 A NOR-only circuit implements . Which structural approach is valid using De Morgan transformations?

Design of logic gates using universal gates Hard
A. NOR each pair, then NOR the two pair outputs
B. Invert each input, then NOR all four inverted inputs
C. NOR all four inputs, then invert only input
D. NOR each pair, then OR the two pair outputs directly

53 A NAND gate is powered from . Its input thresholds are and . A measured input is . How should this input be classified?

Implementation and validation of logic gates Hard
A. Valid logic 0
B. Undefined logic level
C. Short-circuit current state
D. Valid logic 1

54 A function is given by . Which simplified expression can be implemented efficiently with NAND gates?

Design of logic gates using universal gates Hard
A.
B.
C.
D.

55 A combinational circuit output briefly glitches when inputs change from to , even though both stable states should produce the same intended output. Which validation method best identifies the cause?

Implementation and validation of logic gates Hard
A. Increase the supply voltage until the glitch disappears
B. Measure propagation delays along reconvergent paths
C. Replace every gate with an inverter
D. Test only the all-zero input combination

56 A NAND-only implementation of is required. Which expression uses the correct NAND arrangement?

Design of logic gates using universal gates Hard
A.
B.
C.
D.

57 A 2-input NOR gate is connected with both inputs tied together to signal . What function should be verified at the output, and what test distinguishes it from an inverter wiring error?

Implementation and validation of logic gates Hard
A. ; test both inputs independently
B. ; test only
C. ; test only
D. ; test both and

58 Which NAND-only expression implements the 3-input majority function, where the output is 1 when at least two inputs are 1?

Design of logic gates using universal gates Hard
A.
B.
C.
D.

59 When validating a gate, an oscilloscope shows the output high level at with no load but only after connecting four gate inputs. Which parameter is most directly implicated?

Implementation and validation of logic gates Hard
A. Input truth-table ordering
B. Boolean absorption law
C. Output drive capability and fan-out
D. Unused input inversion

60 A NOR gate is to be built using NAND gates only. Which sequence correctly preserves the required polarity?

Design of logic gates using universal gates Hard
A. NAND and , then invert the NAND output twice
B. Invert and with NANDs, then NAND the inverted signals
C. Invert the NAND output once, then invert both inputs
D. NAND and , then connect the result directly to the output
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