Unit 5: Adder Chronicles

I. Orientation: Binary Addition in Combinational Logic

A binary adder is a combinational logic circuit that performs arithmetic addition on binary digits. Its outputs depend only on the present input values, not on previous inputs or stored state. The fundamental binary operation combines input bits and produces a sum bit and, when necessary, a carry bit.

• Binary variables: Each input and output has one of two logic values, 0 or 1.
• Logic convention: Positive logic is assumed, where a higher voltage represents logic 1 and a lower voltage represents logic 0.
• Combinational behavior: The output changes after a propagation delay whenever an input changes.
• Basic operators: AND produces 1 only when all inputs are 1; OR produces 1 when at least one input is 1; XOR produces 1 when inputs are different.
• Adder outputs: S denotes the sum bit, while C or Cout denotes the carry output.
• Boolean notation: + represents OR, adjacency represents AND, and an apostrophe represents NOT. Thus, A'B means NOT A AND B.
• Truth-table basis: All possible input combinations are listed to verify the required Boolean function.
• Hardware assumption: Gate delays, fan-in limits, voltage levels, and loading are ignored during ideal Boolean design but considered during practical validation.

II. Design of a Half Adder: Adding Two Single Bits

A. Definition and Operating Principle

A half adder is a combinational circuit that adds two one-bit binary inputs and produces a one-bit sum and a one-bit carry. It is called “half” because it has no input for a carry generated by a preceding bit position.

• Inputs: A and B are the two binary addends.
• Outputs: S is the sum output and C is the carry output.
• Binary interpretation: The numerical operation is A + B = 2C + S.
• No carry input: The circuit cannot directly add a carry from a lower-order stage.
• Gate requirement: One XOR gate generates S, and one AND gate generates C.

B. Design of a half adder

The half-adder design follows directly from the four possible combinations of A and B.

• Sum function: The sum is 1 when exactly one input is 1, which is the XOR operation.

S = A XOR B

• Carry function: A carry occurs only when both inputs are 1, which is the AND operation.

C = A B

• Canonical sum expression: From the truth table, the sum is also written as:

S = A'B + AB'

• Canonical carry expression: The only carry-producing row is A = 1, B = 1.

C = AB

• Circuit realization: Connect A and B to an XOR gate for S, and connect the same inputs to an AND gate for C.

C. Design Interpretation and Limitations

The half adder demonstrates how Boolean functions map directly to gates, but its missing carry input restricts its use in multibit arithmetic.

• Independent outputs: S and C are generated simultaneously from the same inputs.
• Carry significance: In 1 + 1, the output S = 0 represents the lower bit and C = 1 represents the next binary position.
• Application: Half adders are useful in the least significant position of an adder when no incoming carry exists.
• Limitation: A half adder cannot correctly process A + B + Cin, where Cin is an incoming carry.
• Expansion: A full adder can be constructed from two half adders and one OR gate.

D. Worked Example

For A = 1 and B = 0, the half adder produces a sum of 1 and a carry of 0.

• XOR calculation:

S = 1 XOR 0 = 1

• AND calculation:

C = 1 AND 0 = 0

• Result: 1 + 0 = 01₂, where the carry bit is the more significant 0 and the sum bit is 1.

III. Design of a Full Adder: Including an Incoming Carry

A. Definition and Operating Principle

A full adder is a combinational circuit that adds three one-bit values: two operand bits and an incoming carry. It produces a sum bit and an outgoing carry, allowing several full adders to be connected for multibit binary addition.

• Inputs: A and B are operand bits; Cin is the carry entering from the lower-order position.
• Outputs: S is the current-position sum; Cout is the carry sent to the next position.
• Numerical relationship: The circuit satisfies A + B + Cin = 2Cout + S.
• Cascading: Connecting Cout of one stage to Cin of the next creates a ripple-carry adder.
• Gate-level basis: The sum uses XOR operations; the carry uses AND and OR operations.

B. Design of a full adder

The full-adder truth table contains eight input combinations and identifies whether the total is 0, 1, 2, or 3.

• Sum function: The sum is 1 when an odd number of the three inputs are 1.

S = A XOR B XOR Cin

• Carry function: A carry occurs when at least two inputs are 1.

Cout = AB + ACin + BCin

• Alternative carry form: Let P = A XOR B represent the partial sum and G = AB represent generated carry.

Cout = G + P Cin

Here, P is the propagate term, G is the generate term, and Cin is the incoming carry.

C. Gate-Level Construction

A full adder can be built structurally from two half adders and an OR gate.

• First half adder: Add A and B.

P = A XOR B
C1 = AB

Here, P is the intermediate sum and C1 is the first carry.

• Second half adder: Add the intermediate sum P to Cin.

S = P XOR Cin
C2 = P Cin

Here, S is the final sum and C2 is the second carry.

• Final carry combination: OR the two carry outputs.

Cout = C1 + C2

• Complete structure: The circuit uses two XOR gates, two AND gates, and one OR gate in its basic implementation.
• Carry meaning: C1 is generated by A and B; C2 occurs when the partial sum and incoming carry are both 1.

D. Worked Example

For A = 1, B = 0, and Cin = 1, the total is 1 + 0 + 1 = 2, represented as 10₂.

• Intermediate half-adder outputs:

P = 1 XOR 0 = 1
C1 = 1 AND 0 = 0

• Second half-adder outputs:

S = 1 XOR 1 = 0
C2 = 1 AND 1 = 1

• Final carry:

Cout = C1 OR C2 = 0 OR 1 = 1

• Result: Cout S = 10₂, matching the arithmetic total.

IV. Validation of Combinational Logic: Proving Circuit Behavior

A. Purpose and Validation Principle

Validation of combinational logic confirms that a designed circuit produces the required output for every permitted input combination. The main evidence comes from Boolean equations, truth tables, circuit simulation, and physical measurements.

• Functional requirement: Every input pattern must produce the specified S and carry outputs.
• Exhaustive checking: A circuit with n binary inputs has 2ⁿ possible combinations.
  • A half adder has 2² = 4 combinations.
  • A full adder has 2³ = 8 combinations.
• Reference model: The arithmetic relation provides a direct check:

A + B + Cin = 2Cout + S

For a half adder, Cin is absent or treated as zero.

B. Truth-Table Validation

A truth table validates logic by comparing each circuit output with the expected Boolean result.

• Half-adder check: For A = B = 1, S = A XOR B = 0 and C = AB = 1; this confirms correct binary carry behavior.
• Full-adder check: For A = B = Cin = 1, S = 1 XOR 1 XOR 1 = 1 and Cout = 1; the output 11₂ represents decimal 3.
• Zero-input check: When every input is 0, all outputs must be 0; any 1 indicates a wiring, logic, or measurement fault.
• Parity check: The sum output must be 1 for an odd number of active inputs and 0 for an even number.
• Majority check: The full-adder carry must be 1 whenever at least two of A, B, and Cin are 1.

C. Boolean and Simulation Validation

Algebraic simplification and simulation provide independent confirmation of the truth-table result.

• Equation comparison: Verify that the implemented circuit matches:

Half adder:
S = A XOR B
C = AB

Full adder:
S = A XOR B XOR Cin
Cout = AB + ACin + BCin

• Structural equivalence: For the two-half-adder design, substitute P = A XOR B into Cout = AB + P Cin and compare it with the majority expression.
• Simulation inputs: Apply all binary input patterns in sequence, allowing enough time between changes for propagation delay.
• Observed outputs: Record S and Cout and compare each row with the expected truth table.
• Timing awareness: Temporary glitches may appear because different gates have unequal delays; stable outputs should be sampled after propagation has settled.

D. Hardware Validation and Practical Limitations

Physical testing checks whether the implemented circuit behaves correctly under real electrical conditions.

• Component identification: Confirm the correct XOR, AND, and OR integrated circuits, their supply voltage, and their pin connections before powering the circuit.
• Power integrity: Connect supply and ground correctly; an unpowered or incorrectly powered IC cannot provide meaningful logic results.
• Input definition: Use switches with pull-up or pull-down resistors so inputs do not float between logic 0 and 1.
• Output observation: LEDs, logic probes, or an oscilloscope can display S and Cout; series resistors are required to limit LED current.
• Propagation delay: The output changes a short time after an input transition, so rapid switching can produce an apparently incorrect reading.
• Loading effects: Excessive output current or too many connected inputs can distort voltage levels and violate logic-family specifications.
• Fault isolation: Test one gate or one stage at a time, then compare the measured output with the corresponding truth-table row.
• Scope of validation: Truth tables prove logical correctness under ideal assumptions; voltage thresholds, noise margin, delay, fan-out, and wiring quality determine practical reliability.