Unit 5: Adder Chronicles - Subjective Questions

Definition: A half adder is a combinational logic circuit that performs the addition of two one-bit binary numbers.

• Inputs: and
• Outputs: Sum and Carry
• It does not accept an input carry from a previous stage.

The Boolean expressions are:

The half adder is useful for adding the least significant bits of two binary numbers, but it cannot be directly used for higher-order bit addition because it has no carry-input terminal.

Logic implementation:

• Connect inputs and to an XOR gate to obtain the sum output.
• Connect the same inputs and to an AND gate to obtain the carry output.

The resulting equations are:

The XOR gate produces logic only when the two inputs are different. The AND gate produces logic only when both inputs are . Thus, the two gates together perform one-bit addition.

The truth table of a half adder is:

Verification:

• For , , the result is .
• For , , the result is .
• For , , the result is .
• For , , the result is , giving Sum and Carry .

Therefore, the XOR and AND expressions correctly represent the half-adder operation.

From the truth table, the Sum output is for the input combinations and .

Therefore, the Sum expression in sum-of-products form is:

This is the standard XOR expression:

The Carry output is only for . Hence:

Thus, a half adder can be designed using an XOR gate for Sum and an AND gate for Carry.

Definition: A full adder is a combinational circuit that adds three one-bit binary inputs: two data bits and an input carry.

• Inputs: , , and carry-in
• Outputs: Sum and carry-out

The Boolean expressions are:

Difference from a half adder:

• A half adder has two inputs, while a full adder has three inputs.
• A half adder cannot process an incoming carry, whereas a full adder can.
• Full adders can be cascaded to construct multi-bit binary adders.

A full adder can be constructed using two half adders and one OR gate.

Construction steps:

1. The first half adder adds and .
   • Intermediate Sum:
   • Intermediate Carry:
2. The second half adder adds and .
   • Final Sum:
   • Intermediate Carry:
3. The OR gate combines the two carry outputs:

Therefore:

This arrangement demonstrates that a full adder can be assembled from simpler half-adder circuits.

The full-adder truth table is:

Explanation:

• The Sum output is when an odd number of inputs are .
• The Carry output is when at least two of the three inputs are .
• For inputs , the binary result is , so both Sum and Carry-out are .

The Sum output is for the input combinations:

• , ,
• , ,
• , ,
• , ,

The canonical sum-of-products expression is:

This expression is the odd-parity function and simplifies to:

Thus, the Sum output can be implemented using two cascaded XOR gates.

The Carry-out is for the input combinations , , , and . The canonical expression is:

Grouping and simplifying the terms gives:

An equivalent and commonly used form is:

The first form shows that a carry is generated when any two input bits are . The second form is convenient when implementing the circuit with two half adders.

Conclusion: A half adder is simpler, but a full adder is more practical for arithmetic circuits because it handles carry propagation.

A multi-bit parallel adder is formed by connecting several full adders in cascade.

Method:

• Each full adder adds one corresponding pair of bits from two binary numbers.
• The carry-out of a lower-order full adder is connected to the carry-in of the next higher-order full adder.
• The least significant stage may use a half adder when there is no initial carry, or a full adder with .

For a four-bit adder:

• Stage 0 adds , , and .
• Stage 1 adds , , and the carry from Stage 0.
• This continues through Stage 3.

The final carry is the most significant carry-out. Such a circuit is called a ripple-carry adder because the carry propagates from one stage to the next.

In a full adder, the carry output can arise in two ways:

• Carry generation: If and , a carry is generated regardless of . The generation term is:

• Carry propagation: If exactly one of or is , an incoming carry is passed to the output. The propagation term is:

Therefore, the carry equation is:

or

This concept is important in the analysis and design of fast adders.

The design of a combinational adder generally follows these steps:

1. Identify the inputs and outputs. For a full adder, the inputs are , , and , while the outputs are and .
2. Prepare the truth table for every possible input combination.
3. Derive Boolean expressions for each output from the rows in which the output is .
4. Simplify the expressions using Boolean algebra, Karnaugh maps, or known XOR relationships.
5. Select logic gates corresponding to the simplified equations.
6. Draw the logic diagram and connect the gates appropriately.
7. Validate the circuit by applying all input combinations and comparing the outputs with the truth table.

This systematic procedure can be used for both half-adder and full-adder design.

Validation is the process of checking whether the actual outputs of a designed circuit agree with the expected outputs for every possible input combination.

Validation is necessary because it:

• Confirms that the Boolean equations were derived correctly.
• Detects incorrect gate connections and wiring errors.
• Identifies faulty or damaged logic gates.
• Verifies that the circuit follows its truth table.
• Ensures reliable operation before the circuit is used in a larger system.

For a circuit with binary inputs, all input combinations should be tested. A half adder therefore requires tests, while a full adder requires tests.

A half adder can be validated using digital ICs, a breadboard, switches, LEDs, and a regulated power supply.

Procedure:

1. Place the XOR and AND gate ICs on the breadboard.
2. Connect the power supply and ground terminals according to the IC data sheets.
3. Apply inputs and using switches or logic-level sources.
4. Connect the Sum and Carry outputs to LEDs through suitable current-limiting resistors.
5. Apply the four input combinations: , , , and .
6. Record the LED indications and compare them with the theoretical truth table.

Expected result: The Sum LED glows for and , while the Carry LED glows only for . Any mismatch indicates a wiring, power, component, or logic error.

To validate a full adder:

• Provide three input switches or digital sources for , , and .
• Connect the Sum and Carry-out outputs to indicators such as LEDs or a logic analyzer.
• Apply all eight input combinations in an organized order.
• Record the observed values of and .
• Compare each observation with the theoretical equations:

The circuit is validated only when all eight observed output pairs match the truth table. If a mismatch occurs, check the power connections, IC pin configuration, input levels, gate wiring, and LED polarity.

Both forms are important. A circuit may be theoretically correct but fail practically because of wiring errors, improper voltage levels, damaged components, or unconnected inputs.

Common errors and remedies include:

• Incorrect IC pin connections: Consult the correct data sheet and verify pin numbers.
• Missing power or ground: Connect the required supply and ground pins before testing.
• Floating inputs: Use defined logic levels through switches with pull-up or pull-down resistors.
• LED connected incorrectly: Check LED polarity and use a suitable series resistor.
• Switch bounce: Operate switches carefully or use debouncing circuitry.
• Overloading outputs: Avoid connecting excessive loads to logic-gate outputs.
• Wrong gate type: Confirm whether the circuit requires XOR, AND, or OR gates.
• Loose breadboard connections: Reinsert wires and ICs firmly.

After correction, repeat all input combinations rather than testing only the previously failed case.

For a full adder, the Sum output is for minterms , , , and :

These minterms do not form larger adjacent groups in a three-variable Karnaugh map, so the simplified Sum is:

The Carry output is for minterms , , , and :

Grouping adjacent cells in pairs gives:

Thus, the Karnaugh map confirms the standard full-adder equations and helps reduce unnecessary logic.

Substitute the input values into the full-adder equations.

Sum:

Carry-out:

Therefore, the output is:

This is correct because the decimal value of is , which is represented in binary as .