Unit 3: Introduction to Combinational Logic Circuits and Logic Families - Subjective Questions

Combinational Logic Circuit:

A combinational logic circuit is a digital circuit whose output at any instant depends only on the present combination of inputs and not on any past inputs. It has no memory element.

• Output =
• Built using only logic gates (AND, OR, NOT, etc.)
• Examples: Adders, Multiplexers, Decoders, Encoders.

Difference from Sequential Circuits:

Thus combinational circuits are simpler and faster, while sequential circuits are needed for storage and state-based operations.

Half Adder: A combinational circuit that adds two single-bit binary numbers and produces a Sum and a Carry.

Truth Table:

Boolean Expressions:

Implementation:

• Sum is realized using an XOR gate.
• Carry is realized using an AND gate.

The half adder cannot handle a carry input from a previous stage, which is its main limitation.

Full Adder: A combinational circuit that adds three input bits — two significant bits , and a carry-in — producing Sum and Carry-out.

Truth Table:

Boolean Expressions:

Using Two Half Adders:

• First half adder adds and to give and .
• Second half adder adds and to give final Sum and .
• Final carry: (using an OR gate).

Thus a full adder = 2 Half Adders + 1 OR gate.

Half Subtractor: A combinational circuit that subtracts one bit () from another (), producing a Difference and a Borrow.

Truth Table:

Boolean Expressions:

Working:

• The Difference is produced by an XOR gate.
• The Borrow is generated when and , realized using an AND gate with complemented.

The half subtractor cannot account for a borrow from a previous stage, so it is limited to single-bit subtraction.

Full Subtractor: A combinational circuit that subtracts two bits considering a borrow from the previous stage. It has three inputs , , and two outputs: Difference (D) and Borrow-out ().

Truth Table:

Boolean Expressions:

Implementation:

• Can be built using two half subtractors and an OR gate.
• The difference is obtained by cascading XOR operations, and the borrow-out combines individual borrows via an OR gate.

Digital Comparator: A combinational circuit that compares two binary numbers and determines their relative magnitudes, indicating whether one is greater than, equal to, or less than the other.

1-Bit Comparator Truth Table:

Boolean Expressions:

Working:

• The A=B output uses an XNOR gate.
• The A>B output is high only when .
• The A<B output is high only when .

Comparators are widely used in ALUs, sorting circuits, and process control systems.

2-Bit Comparator: Compares two 2-bit numbers and , producing outputs , , and .

Equality Condition ():

Both bit pairs must be equal:

where denotes XNOR.

Greater Than ():

• MSB of A is 1 and B is 0, OR
• MSBs equal and .

Less Than ():

Working Principle:

• Comparison starts from the most significant bit.
• If MSBs differ, the result is decided immediately.
• If MSBs are equal, the next lower bit determines the result.

This cascading logic can be extended for n-bit comparators, and dedicated ICs like the 7485 implement 4-bit comparison with cascade inputs.

Multiplexer (MUX): A combinational circuit that selects one of many input lines and routes it to a single output line. It is also called a data selector. A MUX with inputs requires select lines.

4-to-1 Multiplexer:

• Inputs:
• Select lines:
• Output:

Selection Table:

Boolean Expression:

Applications:

• Data routing and selection
• Implementing Boolean functions
• Parallel-to-serial conversion
• Logic function generation.

A multiplexer can directly implement any Boolean function of variables using a -to-1 MUX, where the input variables act as select lines and the data inputs are tied to logic 0 or 1 based on the truth table.

Example: Implement using a 4-to-1 MUX.

Truth Table:

Connection:

• Select lines: ,
• (for )
• (for )
• (for )
• (for )

Result: The MUX output directly gives .

Advantage of MUX method:

• A function of variables can be implemented with a -to-1 MUX by using one variable at the data inputs (residue method), reducing hardware.
• Eliminates the need for minimization in many cases.

Demultiplexer (DEMUX): A combinational circuit that takes a single input and routes it to one of many output lines based on the select lines. It performs the reverse operation of a multiplexer and is also called a data distributor.

A 1-to- DEMUX needs select lines.

1-to-4 Demultiplexer:

• Input:
• Select lines:
• Outputs:

Truth Table:

Boolean Expressions:

Applications: Data distribution, serial-to-parallel conversion, and clock demultiplexing.

Decoder: A combinational circuit that converts input lines into a maximum of unique output lines, where only one output is active for each input combination. It essentially decodes coded information.

2-to-4 Line Decoder (active high, with enable E):

• Inputs:
• Enable:
• Outputs:

Truth Table:

Boolean Expressions:

Applications: Memory address decoding, BCD-to-7-segment display driving, and implementing combinational functions.

Encoder: A combinational circuit that performs the reverse operation of a decoder. It converts input lines into coded output lines. Only one input is active (high) at a time.

8-to-3 (Octal-to-Binary) Encoder:

• Inputs: to
• Outputs:

Truth Table:

Boolean Expressions:

Encoders are realized using OR gates. A key limitation is that if two inputs are active simultaneously, the output is invalid — solved by a priority encoder.

Encoder vs Decoder:

Priority Encoder:

A priority encoder is an enhanced encoder that resolves the problem of multiple active inputs. When more than one input is active, it produces the output code corresponding to the highest-priority (usually highest-numbered) input.

Features:

• Assigns priority levels to inputs.
• Includes a valid output (V) bit indicating at least one input is active.
• Example: In a 4-to-2 priority encoder, if and are both high, output corresponds to .

Expression for 4-to-2 priority encoder:

Priority encoders are used in interrupt controllers where multiple requests must be prioritized.

Parity: Parity is an error-detection technique that adds an extra bit (parity bit) to data to make the total number of 1's either even (even parity) or odd (odd parity).

Parity Generator: A circuit that generates the parity bit at the transmitter.

For a 3-bit message :

• Even parity bit:
• Odd parity bit:

Parity Checker: A circuit at the receiver that checks whether the received data (including parity bit) has the correct parity. It produces an error signal if parity is violated.

For received bits (even parity):

• If → data received correctly.
• If → single-bit error detected.

Example: For data with even parity, number of 1's = 2 (even), so . Transmitted word = .

Limitation: Parity can detect single-bit (odd number of) errors but cannot detect even numbers of errors nor correct them.

Logic Family: A group of digital ICs that are fabricated using the same technology and share similar electrical characteristics, allowing them to be interconnected and used together in digital systems.

Types: TTL, ECL, MOS, CMOS, RTL, DTL, etc.

Important Characteristics for Comparison:

• Fan-in: Number of inputs a gate can accept.
• Fan-out: Number of standard gate inputs that a single output can drive.
• Propagation Delay: Time taken for output to respond to a change in input; determines speed.
• Power Dissipation: Power consumed by the gate during operation.
• Noise Margin: Maximum noise voltage tolerated without causing erroneous output.
• Speed-Power Product: Figure of merit = propagation delay × power dissipation (measured in pJ); lower is better.
• Supply Voltage (): Operating voltage.
• Operating Temperature Range.
• Cost and Availability.

These parameters help designers choose the appropriate family for a given application balancing speed, power, and cost.

TTL (Transistor-Transistor Logic): A bipolar logic family that uses multi-emitter transistors at the input and a totem-pole output stage.

Structure of a Standard TTL NAND Gate:

• Input stage: A multi-emitter transistor () whose emitters act as inputs.
• Phase splitter: Transistor that drives the output stage and provides complementary signals.
• Output stage (Totem-pole): Transistors and along with a diode, providing low output impedance for both high and low states.

Operation:

• When any input is LOW: The corresponding emitter of conducts, base of is pulled low, and turn OFF, turns ON → Output HIGH.
• When all inputs are HIGH: The base-collector junction of forward biases, driving and ON, OFF → Output LOW.

This satisfies the NAND condition — output is LOW only when all inputs are HIGH.

Features of TTL:

• Supply voltage
• Good speed and reasonable power dissipation (~10 mW/gate)
• Fan-out typically 10
• Totem-pole output gives fast switching.

CMOS (Complementary Metal-Oxide-Semiconductor): A logic family using both p-channel (PMOS) and n-channel (NMOS) MOSFETs in a complementary configuration.

Structure of a CMOS Inverter:

• Consists of one PMOS transistor (connected to ) and one NMOS transistor (connected to ground) with their gates tied together as the input and drains connected as the output.

Operation:

• When input = LOW (0): PMOS is ON, NMOS is OFF → output pulled to → Output HIGH.
• When input = HIGH (1): PMOS is OFF, NMOS is ON → output pulled to ground → Output LOW.

In both stable states, only one transistor conducts and the other is OFF, so there is no direct conduction path from to ground.

Why CMOS is preferred for low-power applications:

• Negligible static power dissipation: Since no continuous current flows in steady state, power is consumed only during switching (dynamic power ).
• High noise margin (approaches supply rails).
• High packing density and scalability.
• Wide supply voltage range (3V to 15V).

These make CMOS ideal for battery-operated and VLSI applications.

Comparison of Logic Families:

Summary:

• TTL offers good speed but higher power consumption and lower density.
• MOS provides high packing density with low power but is comparatively slow.
• CMOS combines the advantages of very low power, high noise immunity and high density, making it the dominant technology in modern VLSI, though its speed at very high frequencies increases dynamic power.

CMOS is currently the most widely used family in digital ICs.

Fan-in:

• The number of input signals that a logic gate can accept.
• Example: A 3-input AND gate has a fan-in of 3.
• Significance: Determines the complexity a gate can handle at its inputs.

Fan-out:

• The maximum number of standard logic gate inputs that a single output can drive reliably without degrading performance.
• Example: TTL typically has a fan-out of about 10.
• Significance: Exceeding fan-out causes logic level degradation and slower switching.

Noise Margin:

• The maximum noise voltage that can be added to the input signal without causing an incorrect output.
• Defined for both HIGH and LOW states:
  
  
• Significance: Higher noise margin means better immunity to electrical noise.

Propagation Delay:

• The time interval between the application of an input change and the resulting change in output.
• Measured as the average of and .
• Significance: Determines the maximum operating speed of the circuit; lower delay = faster circuit.

Together these parameters define the reliability, drive capability, noise immunity, and speed of a logic family.

Implementing Functions Using a Decoder:

An -to- decoder generates all minterms of variables. Since any Boolean function can be expressed as a sum of minterms, the required minterm outputs of the decoder are combined using an OR gate.

Example: Implement using a 3-to-8 decoder.

• Connect to decoder inputs.
• OR together outputs :
  

Multiple functions can share the same decoder using separate OR gates.

Building Larger Circuits from Smaller Ones (Cascading):

• Larger Decoders: A 3-to-8 decoder can be built using two 2-to-4 decoders. The extra input acts as an enable — it activates one decoder for the lower half and the other for the upper half of addresses.

• Larger Multiplexers: An 8-to-1 MUX can be constructed from two 4-to-1 MUXes and one 2-to-1 MUX. The two 4-to-1 MUXes handle groups of inputs, and the final 2-to-1 MUX selects between them using the most significant select line.

Advantage: Modular expansion allows building wide address decoders and large data selectors from readily available smaller ICs, saving design effort and cost.