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Unit 4: Introduction to Sequential Logic Circuits - Practice Quiz

ECE213 — Digital Electronics 60 Questions
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1 What is the key feature that distinguishes a sequential circuit from a combinational circuit?

Basic sequential circuits Easy
A. It uses only logic gates
B. It has no feedback path
C. It depends only on present inputs
D. It has memory and depends on past inputs

2 Which element is essential in a sequential circuit but absent in a purely combinational circuit?

Basic sequential circuits Easy
A. AND gate
B. Multiplexer
C. Inverter
D. Memory (storage) element

3 In an SR latch, which input combination is considered invalid (forbidden)?

SR-latch Easy
A.
B.
C.
D.

4 What does the SR latch do when and ?

SR-latch Easy
A. Sets the output to 1
B. Resets the output to 0
C. Holds the previous state
D. Toggles the output

5 The letters 'S' and 'R' in an SR latch stand for which functions?

SR-latch Easy
A. Store and Retrieve
B. Send and Receive
C. Set and Reset
D. Shift and Rotate

6 A D latch is often used to eliminate which problem of the SR latch?

D-latch Easy
A. The invalid state condition
B. The hold state
C. The reset operation
D. The set operation

7 When a D latch is enabled, what value does its output take?

D-latch Easy
A. Always 0
B. Always 1
C. The complement of
D. The value of the input

8 A D flip-flop is commonly used to perform which function in digital systems?

D flip-flop Easy
A. Store one bit of data
B. Multiply two signals
C. Add two binary numbers
D. Compare two inputs

9 The characteristic equation of a D flip-flop is given by which expression?

D flip-flop Easy
A.
B.
C.
D.

10 What does a JK flip-flop do when both inputs are high ()?

JK flip-flop Easy
A. Sets the output to 1
B. Resets the output to 0
C. Holds the output
D. Toggles the output

11 The JK flip-flop is considered an improvement over the SR flip-flop because it does what?

JK flip-flop Easy
A. Removes the hold state
B. Removes the invalid input condition
C. Removes the clock input
D. Removes the need for feedback

12 In a JK flip-flop, what happens when and ?

JK flip-flop Easy
A. Toggle
B. No change (hold state)
C. Reset to 0
D. Set to 1

13 What does the 'T' in a T flip-flop stand for?

T flip-flop Easy
A. Trigger
B. Timer
C. Toggle
D. Transfer

14 In a T flip-flop, what happens to the output when on the active clock edge?

T flip-flop Easy
A. The output is set to 1
B. The output holds
C. The output is reset to 0
D. The output toggles

15 A T flip-flop is most easily obtained by connecting which inputs of a JK flip-flop together?

T flip-flop Easy
A. and clock
B. and
C. and
D. and clock

16 To convert a D flip-flop into a T flip-flop, the input should be connected to which expression?

Conversion of basic flip-flops Easy
A.
B.
C.
D.

17 When converting one flip-flop into another, which table is used to determine the required input logic?

Conversion of basic flip-flops Easy
A. Timing diagram
B. Excitation table
C. Truth table of a gate
D. Karnaugh map only

18 A master-slave flip-flop is primarily built to solve which problem?

Master-Slave Flip-Flop Easy
A. The race-around condition
B. The hold-state problem
C. The power consumption problem
D. The invalid input condition

19 A master-slave flip-flop is made up of how many latches connected together?

Master-Slave Flip-Flop Easy
A. Four latches
B. One latch
C. Three latches
D. Two latches

20 An edge-triggered flip-flop changes its output at which point of the clock signal?

Edge triggering Easy
A. At the high level
B. At the low level
C. At any random time
D. At the rising or falling edge

21 In a NAND-based SR latch, the inputs are active-low ( and ). Which input combination produces the invalid (forbidden) state?

SR-latch Medium
A.
B.
C.
D.

22 A NOR-based SR latch currently stores . If the inputs are applied, what is the next state of ?

SR-latch Medium
A. Invalid state
B. toggles
C. (hold)
D. (reset)

23 A gated D-latch has enable . If the input changes several times while , how does the output behave?

D-latch Medium
A. follows continuously
B. latches the first value of
C. latches the last value before went high
D. ignores entirely

24 How is a D-latch typically constructed from an SR latch to eliminate the invalid input condition?

D-latch Medium
A. Tie permanently
B. Connect to and to with feedback
C. Connect to and to
D. Connect to both and

25 A positive-edge-triggered D flip-flop has at the rising edge and becomes 0 shortly after. What is after this clock edge?

D flip-flop Medium
A. is undefined
B. toggles
C.
D.

26 The characteristic equation of a D flip-flop is:

D flip-flop Medium
A.
B.
C.
D.

27 A JK flip-flop has . What operation does it perform at each active clock edge?

JK flip-flop Medium
A. Set the output to 1
B. Hold the output
C. Reset the output to 0
D. Toggle the output

28 The characteristic equation of a JK flip-flop is:

JK flip-flop Medium
A.
B.
C.
D.

29 A JK flip-flop currently has . If is applied at the clock edge, what is ?

JK flip-flop Medium
A. Undefined
B.
C.
D.

30 A T flip-flop with is driven by a clock of frequency . What is the frequency of the output ?

T flip-flop Medium
A.
B.
C.
D.

31 The characteristic equation of a T flip-flop is:

T flip-flop Medium
A.
B.
C.
D.

32 To convert a JK flip-flop into a D flip-flop, how should the and inputs be connected in terms of ?

Conversion of basic flip-flops Medium
A.
B.
C.
D.

33 To convert a D flip-flop into a T flip-flop, what expression must drive the input?

Conversion of basic flip-flops Medium
A.
B.
C.
D.

34 To convert a JK flip-flop into a T flip-flop, how are and connected?

Conversion of basic flip-flops Medium
A.
B.
C.
D.

35 When converting a T flip-flop into a D flip-flop, what should the input be driven by?

Conversion of basic flip-flops Medium
A.
B.
C.
D.

36 In a master-slave JK flip-flop, when is the data actually transferred to the slave (final) output?

Master-Slave Flip-Flop Medium
A. Only when both master and slave are triggered simultaneously
B. Continuously while the clock is high
C. On the falling edge, when the master is disabled and slave enabled
D. On the rising edge, when both stages are enabled

37 The primary purpose of the master-slave configuration in a JK flip-flop is to:

Master-Slave Flip-Flop Medium
A. Increase the switching speed of the flip-flop
B. Reduce the number of gates required
C. Prevent race-around condition when
D. Allow level triggering instead of edge triggering

38 Which condition is most likely to cause the race-around problem in a level-triggered JK flip-flop?

Edge triggering Medium
A. with a very narrow clock pulse
B. with a narrow clock pulse
C. with a wide clock pulse
D. with clock pulse width greater than the propagation delay

39 What is the key behavioral difference between an edge-triggered flip-flop and a level-triggered latch?

Edge triggering Medium
A. Both respond only to clock transitions equally
B. The flip-flop is transparent during the active level, while the latch responds only at transitions
C. The flip-flop changes state only at a clock transition, while the latch is transparent during the active level
D. Both are transparent while the clock is active

40 In a positive-edge-triggered flip-flop, the input data must remain stable for a short interval before the clock edge. This requirement is called the:

Edge triggering Medium
A. Clock skew
B. Hold time
C. Propagation delay
D. Setup time

41 A NOR-based SR latch has inputs and . Both and are applied simultaneously and then both are switched to at exactly the same instant. What is the resulting state?

SR-latch Hard
A. Outputs hold the previous state throughout
B. Outputs oscillate indefinitely and never settle
C. Both outputs are during , and the final state is unpredictable (race condition)
D. Both outputs are during , and it settles to Set state

42 For a NAND-based SR latch (active-low ), which input combination is forbidden and what does it force on the outputs?

SR-latch Hard
A. , forcing
B. , forcing
C. , forcing
D. , forcing

43 A gated D-latch is transparent when its enable . If changes value multiple times while and then goes to , what value is stored?

D-latch Hard
A. The complemented last value of
B. The logical average of all values during
C. The value of present at the instant transitions to
D. The first value of seen after became

44 What is the primary functional difference that distinguishes a D-latch from an SR-latch?

D-latch Hard
A. The D-latch eliminates the forbidden state by tying through an inverter
B. The D-latch requires two clock phases while SR needs one
C. The D-latch cannot store data whereas SR can
D. The D-latch responds only to clock edges, SR to levels

45 A positive-edge-triggered D flip-flop has setup time ns and hold time ns. Data changes ns before the clock edge. What is the outcome?

D flip-flop Hard
A. Setup violation, output may become metastable
B. No violation, output reliably captures new data
C. Hold violation, output latches old data
D. Clock skew violation, output freezes

46 A D flip-flop is configured with its output fed back to input . On each rising clock edge, what does the output do?

D flip-flop Hard
A. Produces a constant logic
B. Toggles, dividing the clock frequency by 2
C. Follows the clock level directly
D. Holds the same value indefinitely

47 For a JK flip-flop, the characteristic equation is . If and continuously, what is ?

JK flip-flop Hard
A. (set)
B. (hold)
C. (toggle)
D. (reset)

48 A simple level-triggered (non-master-slave) JK flip-flop with suffers from which problem when the clock pulse is wider than the propagation delay?

JK flip-flop Hard
A. Race-around condition causing multiple toggles per pulse
B. Setup time violation on the J input
C. Loss of the hold condition entirely
D. Permanent latch-up in the set state

49 A T flip-flop starts at . The input sequence is applied over four consecutive clock edges. What is the final value of ?

T flip-flop Hard
A. is undefined
B. oscillates
C.
D.

50 The characteristic equation of a T flip-flop is best expressed as which of the following?

T flip-flop Hard
A.
B.
C.
D.

51 To convert a D flip-flop into a JK flip-flop, what excitation logic must drive the input?

Conversion of basic flip-flops Hard
A.
B.
C.
D.

52 When converting a JK flip-flop into a D flip-flop, which excitation values for and are required in terms of ?

Conversion of basic flip-flops Hard
A. and
B. and
C. and
D. and

53 To convert a T flip-flop into a JK flip-flop, the excitation input should be driven by which expression?

Conversion of basic flip-flops Hard
A.
B.
C.
D.

54 For converting a JK flip-flop into a T flip-flop, what should and be tied to?

Conversion of basic flip-flops Hard
A.
B.
C.
D. Both and tied to

55 In a master-slave JK flip-flop, the master is enabled when clock is high and the slave when clock is low. This flip-flop can still suffer from which anomaly?

Master-Slave Flip-Flop Hard
A. Setup violations that cannot be avoided by any design
B. Complete loss of the toggle function
C. "1s catching" / "0s catching" from spurious pulses on J or K during the high phase
D. Race-around toggling multiple times per clock

56 In a master-slave configuration, when is the new data actually presented at the external output ?

Master-Slave Flip-Flop Hard
A. Continuously while the clock is high
B. Only after two full clock cycles
C. On the falling (trailing) edge, when the slave copies the master
D. On the rising edge, when the master latches input

57 What is the fundamental advantage of an edge-triggered flip-flop over a master-slave flip-flop built from latches?

Edge triggering Hard
A. It requires no clock signal to operate
B. It eliminates the need for setup and hold times
C. It samples input only within a narrow window around the edge, avoiding ones-catching glitches
D. It can store two bits per clock cycle

58 A negative-edge-triggered D flip-flop receives a clock and data as follows: during a rising edge but during the subsequent falling edge. What does become?

Edge triggering Hard
A. , captured on the rising edge
B. , captured on the falling edge
C. holds its previous value
D. is metastable due to conflicting edges

59 In an edge-triggered flip-flop, the hold time requirement is best described as the interval during which:

Edge triggering Hard
A. The output takes to settle after the edge
B. Data must remain stable before the active clock edge
C. Data must remain stable after the active clock edge
D. The clock must remain high

60 A negative-edge-triggered JK flip-flop starts at . Inputs across four falling edges are: . What is the final ?

JK flip-flop Hard
A.
B. is undefined
C. toggles endlessly
D.
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