Unit 4 - Practice Quiz

CSE211 60 Questions
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1 What does the acronym HDL stand for in the context of digital design?

History Easy
A. Hardware Description Language
B. High-level Design Language
C. High Definition Logic
D. Hardware Design Logic

2 Which phase of the HDL design flow involves converting the HDL code into a gate-level netlist?

Typical HDL-based Design Flow (Design, Simulation, Synthesis, Verification) Easy
A. Synthesis
B. Verification
C. Design Entry
D. Simulation

3 A fundamental difference between an HDL and a typical software programming language like C is that HDLs are designed to model...

Comparison with Software Programming Languages Easy
A. Object-oriented principles
B. Parallelism and concurrency
C. Sequential execution only
D. User interface design

4 In Verilog, what is the fundamental building block used to describe a digital component?

Verilog Easy
A. class
B. procedure
C. module
D. function

5 What does the statement R1 ← R2 signify in Register Transfer Language (RTL)?

Register Transfer Language Easy
A. The contents of R1 and R2 are added together.
B. The contents of register R1 are transferred to register R2.
C. The contents of register R2 are transferred to register R1.
D. The contents of R1 and R2 are swapped.

6 What is a 'bus' in the context of a digital computer system?

Bus and Memory Transfer Easy
A. A software program for system diagnostics.
B. A type of high-speed memory.
C. A component that performs arithmetic operations.
D. A set of common wires used for communication between multiple components.

7 Which of the following is considered a logic micro-operation?

Micro operations (Arithmetic, logic, shift) Easy
A. INCREMENT
B. ADD
C. XOR
D. SUBTRACT

8 What is the main purpose of a shift register?

Shift Register Easy
A. To count clock pulses.
B. To perform addition of binary numbers.
C. To store and move data bit-by-bit.
D. To decode instructions.

9 In a full adder circuit, what are the three inputs?

Addition Easy
A. Two input bits and a Carry In
B. Three input bits
C. One input bit, a Carry In, and a Sum
D. Two input bits and a Carry Out

10 Booth's algorithm is particularly efficient for multiplying which type of numbers?

Booth Multiplication Easy
A. Unsigned binary numbers
B. Decimal numbers
C. Signed binary numbers in two's complement
D. Floating-point numbers

11 In the HDL design flow, what is the purpose of simulation?

Typical HDL-based Design Flow (Design, Simulation, Synthesis, Verification) Easy
A. To convert the design into physical transistors.
B. To check the functional correctness of the design before synthesis.
C. To generate the final circuit layout.
D. To formally prove the design has no bugs.

12 A micro-operation is defined as an elementary operation executed on...

Register Transfer and Micro Operation Easy
A. the entire memory.
B. an I/O device.
C. data stored in registers.
D. the operating system.

13 The operation R1 ← M[AR] represents which of the following?

Bus and Memory Transfer Easy
A. A logical operation
B. A memory read operation
C. A memory write operation
D. An arithmetic operation

14 To perform the subtraction A - B using two's complement arithmetic, the hardware actually calculates:

Subtraction Easy
A. A + (1's complement of B)
B. A + (2's complement of B)
C. B + (2's complement of A)
D. NOT A + B

15 What was a major limitation of early digital design methods like schematic capture that led to the evolution of HDLs?

Evolution Easy
A. They could only be used for analog circuits.
B. Inability to represent simple logic gates.
C. Circuits designed were too slow.
D. Difficulty in managing and modifying large, complex designs.

16 In Verilog, which data type is used to represent a physical connection between components, like a wire?

Verilog Easy
A. wire
B. real
C. integer
D. reg

17 What does a control function, like P: in the statement P: R2 ← R1, represent?

Register Transfer Language Easy
A. A condition that must be true for the operation to occur.
B. A program counter.
C. A pointer to memory.
D. A power-on signal.

18 Which type of shift micro-operation fills the vacated bit position with a 0?

Micro operations (Arithmetic, logic, shift) Easy
A. Logical Shift
B. Bi-directional Shift
C. Arithmetic Shift
D. Circular Shift (Rotate)

19 In the basic shift-and-add algorithm for binary multiplication, how many bits is the partial product typically shifted in each step?

Multiplication Algorithm Easy
A. 2 bits
B. 0 bits
C. 1 bit
D. 4 bits

20 What is the primary goal of the 'Verification' stage in the HDL design flow?

Typical HDL-based Design Flow (Design, Simulation, Synthesis, Verification) Easy
A. To choose the HDL language (Verilog or VHDL).
B. To convert HDL code to gates.
C. To write the initial HDL code.
D. To ensure the final synthesized design meets all requirements (timing, functionality, power).

21 A designer completes a functional simulation of a Verilog module, and it passes all test cases. However, after synthesis and implementation on an FPGA, the circuit fails at the target clock frequency. What is the most likely reason for this discrepancy?

Typical HDL-based Design Flow Medium
A. The functional simulation did not cover all possible input combinations.
B. The synthesis tool has a bug and generated an incorrect netlist.
C. The design has timing violations (e.g., setup/hold time violations) that are not checked during functional simulation.
D. The Verilog code contained a syntax error.

22 Using Booth's algorithm to multiply a multiplicand by the 2's complement multiplier 10110. What is the sequence of arithmetic micro-operations performed? (Assume an initial appended bit of 0).

Booth Multiplication Medium
A. Subtract, No-op, Add, Subtract, Add
B. Subtract, Add, Subtract, Add, No-op
C. Add, Subtract, No-op, Add, Subtract
D. No-op, Subtract, Add, Subtract, No-op

23 Consider the following Verilog code snippet inside an always @(posedge clk) block. If a is initially 1 and b is initially 0, what are the values of a and b after one positive clock edge?
verilog
a = b;
b = a;

Verilog Medium
A. a = 0, b = 0
B. a = 1, b = 1
C. a = 0, b = 1
D. a = 1, b = 0

24 The RTL statement T1: R2 <- R1, T2: R1 <- R2 is intended to swap the contents of registers R1 and R2 using two sequential control signals (T1 then T2). What is the actual result of this sequence of operations?

Register Transfer Language Medium
A. Both registers will end up with the original value of R2.
B. The contents of R1 and R2 are successfully swapped.
C. The final contents of both registers will be the original value of R1.
D. The contents of R1 are copied to R2, and R1's original value is lost.

25 Which sequence of micro-operations correctly implements the 2's complement subtraction R1 <- R1 - R2?

Micro operations (Arithmetic, logic, shift) Medium
A. R2 <- not(R2), then R1 <- R1 + R2
B. R1 <- not(R1) + 1, then R1 <- R1 + R2
C. R2 <- not(R2) + 1, then R1 <- R1 + R2
D. R1 <- R1 + not(R2), then R1 <- R1 + 1

26 To perform a memory write operation that stores the content of register R1 into memory location X, which sequence of micro-operations is correct?

Bus and Memory Transfer Medium
A. MBR <- X, MAR <- R1, Write
B. MAR <- X, Write, MBR <- R1
C. MAR <- X, MBR <- R1, Write
D. R1 <- M[X], Write

27 What is the most fundamental difference between the execution model of an HDL like Verilog and a conventional software programming language like C?

Comparison with Software Programming Languages Medium
A. HDLs support object-oriented programming, while C does not.
B. HDLs have a stricter type system than C to prevent hardware errors.
C. C code compiles to machine code, while HDL code is interpreted by a simulator.
D. HDLs describe inherently concurrent hardware operations, whereas C describes a sequence of instructions executed one at a time.

28 A 4-bit universal shift register has two control inputs, s1 and s0, to determine its function. If the mapping is 00=hold, 01=shift-right, 10=shift-left, 11=parallel load, what control sequence is needed to load the value 1011 and then shift it twice to the right?

Shift Register Medium
A. Set s1s0 to 11 for one clock cycle, then to 10 for two cycles.
B. Set s1s0 to 11 for one clock cycle, then to 01 for two cycles.
C. Set s1s0 to 11 for one clock cycle, then to 00 for two cycles.
D. Set s1s0 to 01 for two clock cycles, then to 11 for one cycle.

29 When multiplying two 4-bit unsigned binary numbers using a standard shift-and-add hardware multiplier, what is the maximum size (in bits) required for the accumulator register that holds the partial product?

Multiplication Algorithm Medium
A. 4 bits
B. 8 bits
C. 5 bits
D. 16 bits

30 What is the primary output of the logic synthesis stage in a typical HDL-based design flow?

Typical HDL-based Design Flow Medium
A. A functionally correct simulation waveform.
B. A gate-level netlist representing the hardware structure.
C. A set of routing and placement information for an FPGA.
D. A high-level behavioral model of the system.

31 In Verilog, what hardware will be inferred by a synthesizer for an always block with an incomplete if-else or case statement (i.e., not all possible conditions are covered)?

Verilog Medium
A. A multiplexer
B. A tri-state buffer
C. A latch
D. A syntax error will be generated

32 What operation is described by the conditional Register Transfer Language statement (K'T + KT'): R1 <- R1 ⊕ R2?

Register Transfer Language Medium
A. R1 is XORed with R2 only when control signals K and T are both 1.
B. R1 is XORed with R2 when K and T have different values (K=0, T=1 or K=1, T=0).
C. R1 is XORed with R2 only when control signals K and T are both 0.
D. R1 is XORed with R2 when K=1 or T=1.

33 In a processor with a common bus system for 16 registers of 32 bits each, what is the minimum number of selection lines required for the multiplexers that select the source register to place data on the bus?

Bus and Memory Transfer Medium
A. 32 lines
B. 5 lines
C. 16 lines
D. 4 lines

34 An 8-bit register contains the value 10110101. What will be the value in the register after an arithmetic shift right operation?

Micro operations (Arithmetic, logic, shift) Medium
A. 01011010
B. 11011010
C. 10110100
D. 00110101

35 In a 4-bit ripple-carry adder used to add A=1011 and B=0110, what are the carry-in () and carry-out () values for the full adder at the most significant bit position (bit 3)?

Addition, Subtraction Medium
A. ,
B. ,
C. ,
D. ,

36 The introduction of Hardware Description Languages (HDLs) marked a major shift from schematic capture-based design. What key capability did HDL-based synthesis provide that was difficult to achieve with schematics?

History, Evolution Medium
A. The creation of a visual representation of the circuit.
B. The automatic optimization of a design based on constraints like area and timing.
C. The ability to use standard logic gates in a design.
D. The simulation of analog signal behavior in the circuit.

37 Using Booth's algorithm to multiply by the 2's complement number 0110 (+6). Let the multiplicand be M. What is the equivalent arithmetic operation represented by the algorithm?

Booth Multiplication Medium
A.
B.
C.
D.

38 A micro-operation is specified by the statement R1 <- R1 + R2' + 1. This operation is most commonly used for which task?

Register Transfer and Micro Operation Medium
A. Subtracting the content of R2 from R1.
B. Adding two unsigned numbers.
C. Calculating the average of R1 and R2.
D. Incrementing R1 and R2 simultaneously.

39 Which logic micro-operation can be used to selectively set specific bits of a register to 1 without affecting the other bits?

Micro operations (Arithmetic, logic, shift) Medium
A. Logical OR
B. Logical NOT
C. Logical XOR
D. Logical AND

40 In the hardware implementation of a shift-and-add multiplier for two 4-bit unsigned numbers, A (multiplicand) and Q (multiplier), the algorithm proceeds in cycles. What happens during a single cycle if the current LSB of Q is 1?

Multiplication Algorithm Medium
A. The multiplicand A is added to the accumulator, and the combined accumulator-Q register is shifted left.
B. The multiplicand A is added to the accumulator, and the combined accumulator-Q register is shifted right.
C. The multiplicand A is subtracted from the accumulator, and the Q register is shifted right.
D. The accumulator is cleared to zero, and the Q register is shifted right.

41 When multiplying two 4-bit 2's complement numbers, Multiplicand M = -8 (1000) and Multiplier Q = -3 (1101), using the standard Booth's algorithm, what is the final 8-bit product [A,Q]? Assume an 8-bit accumulator A and 8-bit representation for M.

Booth Multiplication Hard
A. 11101000 (-24)
B. 11111111 (-1)
C. The algorithm produces an incorrect result for the most negative number 1000.
D. 00011000 (+24)

42 A Verilog module contains an initial block that initializes a register and a timing constraint file specifying a maximum clock period. How will a typical synthesis tool for an FPGA handle this combination?

Typical HDL-based Design Flow Hard
A. It will synthesize the logic without the initial block, and then fail post-synthesis timing analysis if the constraints are not met.
B. It will interpret the initial block as a testbench-only construct, ignore it, and synthesize the remaining logic without timing constraints.
C. It will generate a synthesis error because initial blocks are not synthesizable and will ignore the timing constraints until after synthesis.
D. It will synthesize the initial block into a power-on-reset circuit, and use the timing file to guide optimization for meeting the specified clock speed during logic mapping.

43 Consider the following Verilog always block. How does its execution model and synthesized hardware fundamentally differ from a similar-looking if-else structure within a function in a C program?
verilog
always @(posedge clk) begin
if (sel)
q <= a;
else
q <= b;
end

Comparison with Software Programming Languages Hard
A. There is no fundamental difference; both are sequential decision-making constructs that execute on a trigger.
B. The Verilog code is only for simulation and cannot be directly translated to hardware, unlike the C code which is compiled to machine instructions.
C. The Verilog code implies a state machine that transitions based on sel, while the C code is a simple conditional branch.
D. The Verilog code describes a concurrent hardware structure (a multiplexer feeding a flip-flop) whose state is captured at a clock edge, whereas the C code describes a sequential set of instructions for a processor.

44 Analyze the following Verilog code snippet intended to implement a two-stage pipeline. What is the actual behavior of q2 at each positive clock edge due to the type of assignments used?
verilog
reg q1, q2;
always @(posedge clk) begin
q1 = din;
q2 = q1;
end

Verilog Hard
A. q2 gets the value that q1 had in the previous clock cycle.
B. The code creates a combinational loop, and the behavior is unpredictable.
C. q2 is a two-cycle delayed version of din.
D. q2 gets the same value as din in the same clock cycle.

45 The RTL statement K: R1 ← R1 + R2, AR ← AR + 1 describes a micro-operation. What does this statement imply about the underlying hardware data path?

Register Transfer Language Hard
A. The data path requires a shared ALU that first computes R1 + R2 and then computes AR + 1.
B. A single control signal K triggers two independent arithmetic operations whose results are loaded into R1 and AR concurrently in the same clock cycle.
C. The operations must occur in two separate, sequential clock cycles controlled by signal K.
D. This is an invalid RTL statement as two destination registers cannot be updated in the same control step.

46 To execute the instruction ADD R1, [AR] (RTL: R1 ← R1 + M[AR]) in a single-bus architecture, what is the most efficient, minimal sequence of micro-operations? Assume the ALU can take one operand from a register (like R1) and another from the bus via a temporary register (DR).

Bus and Memory Transfer Hard
A. 1. Bus ← M[AR], DR ← Bus 2. Bus ← R1 3. R1 ← Bus + DR
B. 1. R1 ← R1 + M[AR]
C. 1. DR ← M[AR] 2. R1 ← R1 + DR
D. 1. Bus ← AR 2. DR ← M 3. Bus ← R1 4. R1 ← R1 + DR

47 In the multiplication of two 4-bit unsigned integers, M = 0110 (6) and Q = 0101 (5), using the standard add-and-shift algorithm, what are the contents of the 4-bit Accumulator (A) and Q register after the 3rd cycle (i.e., after the third add/no-add decision and the third shift)?

Multiplication Algorithm Hard
A. A = 0001, Q = 1001
B. A = 0011, Q = 1100
C. A = 0111, Q = 1100
D. A = 0011, Q = 0010

48 You need to compute Y = 7A - B where A and B are registers, using only shift, add, and subtract micro-operations. Which sequence is most efficient in terms of the number of micro-operations?

Micro operations (Arithmetic, logic, shift) Hard
A. T ← shl(A, 2); T ← T + A; T ← shl(T, 1); Y ← T - B
B. Y ← A; Y ← Y + A; Y ← Y + A; ... (7 times); Y ← Y - B
C. T ← shl(A, 3); T ← T - A; Y ← T - B
D. T1 ← -B; Y ← 7*A; Y ← Y + T1

49 For which of the following 8-bit 2's complement multipliers will Radix-2 Booth's algorithm perform the maximum possible number of arithmetic operations (additions/subtractions)?

Booth Multiplication Hard
A. 10000000 (-128)
B. 11111111 (-1)
C. 01010101 (85)
D. 00110011 (51)

50 A critical bug in a cache coherency protocol is found post-silicon. The bug only occurs in a complex corner case that was missed by 100% code and functional coverage in simulation. Which verification technique would have been most likely to identify this type of bug?

Typical HDL-based Design Flow Hard
A. FPGA-based emulation to run more software tests.
B. Gate-level simulation with back-annotated timing.
C. Formal verification using model checking.
D. Increasing the random simulation seed count.

51 Given the inherent non-determinism in Verilog's event scheduler for events at the same simulation time, what are the possible final values for register c in the following code block?
verilog
initial begin
reg a, b, c;
a = 0;
fork
#1 a = 1;
#1 b = a;
join
c = b;
end

Verilog Hard
A. 0 or 1, depending on simulator implementation
B. 1 only
C. 0 only
D. X (unknown)

52 In a 4-bit carry-lookahead adder, the carry-out is generated by the logic function . What is the primary reason this design is faster than a 4-bit ripple-carry adder for the worst-case delay?

Addition, Subtraction Hard
A. The propagate () and generate () signals have a smaller fan-out than the carry signals in a ripple-carry adder.
B. It uses fewer total logic gates, reducing area and propagation delay.
C. It operates on a different number system, like carry-save, which is inherently faster.
D. It calculates all carry bits in parallel directly from the P and G inputs, avoiding the serial dependency of the carry chain.

53 In a system with multiple registers (R0, R1, R2) connected to a common data bus, why is it functionally mandatory to use tri-state buffers on each register's output path to the bus?

Bus and Memory Transfer Hard
A. To amplify the register signals to drive the capacitive load of the bus.
B. To reduce system power consumption by disconnecting inactive registers.
C. To allow data to flow bidirectionally into and out of the registers on the same set of wires.
D. To prevent bus contention, where multiple registers driving opposite logic levels ('1' and '0') would cause a short circuit.

54 A processor's control unit must generate the 'load enable' signal for register R1. The register is updated by the following micro-operations, which are active during different time steps (T1, T2, T3) and under certain conditions (x, y):
xT1: R1 ← R2
y'T2: R1 ← R1 + R2
* T3: R1 ← 0
What is the correct Boolean expression for the control signal Load_R1?

Register Transfer Language Hard
A. Load_R1 = xT1 + y'T2
B. Load_R1 = (x AND T1) OR (NOT y AND T2) OR T3
C. Load_R1 = (x OR T1) AND (y' OR T2) AND T3
D. Load_R1 = x + T1 + y' + T2 + T3

55 An 8-bit register contains the 2's complement value for -53 (11001011). What are the contents of the register after a 1-bit arithmetic shift right (ashr), a 1-bit logical shift right (lshr), and a 1-bit rotate right (ror) are performed on this original value, respectively?

Micro operations (Arithmetic, logic, shift) Hard
A. ashr: 01100101, lshr: 01100101, ror: 11100101
B. ashr: 11100101, lshr: 01100101, ror: 11100101
C. ashr: 11100101, lshr: 01100101, ror: 01100101
D. ashr: 11100101, lshr: 11100101, ror: 01100101

56 A synthesis tool is processing a combinational Verilog always @(*) block. Under which of these circumstances will it most likely infer a transparent latch, a component often avoided in synchronous designs?

Typical HDL-based Design Flow Hard
A. When a case statement inside the block includes a default clause.
B. When the block contains a for loop with a constant number of iterations.
C. When an output signal is not assigned a value in all possible conditional branches (e.g., an if statement is missing an else clause).
D. When a non-blocking assignment (<=) is used instead of a blocking assignment (=).

57 What is a key constraint on Verilog's generate for construct that fundamentally distinguishes its purpose and implementation from a for loop in a language like C?

Comparison with Software Programming Languages Hard
A. The loop's iteration count must be a constant that can be determined at synthesis time, as synthesis unrolls the loop to create static, parallel hardware structures.
B. The generate for loop requires a special clock signal to sequence through its 'iterations'.
C. The generate for loop is executed at runtime to dynamically create hardware.
D. The generate for loop's variable (genvar) cannot be used in expressions inside the loop body.

58 A 4-bit universal shift register has control inputs for its function (00:Hold, 01:Shift-Right, 10:Shift-Left, 11:Parallel-Load). To implement the operation R ← (R / 4) + 8 on the 4-bit unsigned value in register R, what is the most efficient sequence of operations? Assume the parallel inputs are wired to a constant value 1000 (8).

Shift Register Hard
A. The operation requires an external ALU and cannot be done with just these functions.
B. 1. Shift-Right; 2. Shift-Right; Then add 8 using a sequence of increments.
C. 1. Parallel-Load; 2. Shift-Right; 3. Shift-Right
D. 1. Shift-Right; 2. Shift-Right; 3. Parallel-Load

59 What was the primary conceptual leap that enabled early HDLs like VHDL and Verilog to dramatically increase design productivity over previous methods like schematic capture?

History, Evolution Hard
A. They introduced object-oriented principles, which simplified the design of reusable components.
B. They enabled the practical application of logic synthesis, allowing designers to work at a behavioral (RTL) level of abstraction instead of a structural (gate) level.
C. They were the first methods to be standardized by the IEEE, ensuring tool compatibility.
D. They integrated simulation and design into a single language, which was not possible with schematics.

60 In Radix-4 Booth's algorithm, the multiplier bits are examined in overlapping groups of three () to determine the operation. Which bit grouping results in the operation "add 2 times the multiplicand" (i.e., perform Accumulator ← Accumulator + 2M) before the 2-bit shift?

Booth Multiplication Hard
A. 011
B. 010
C. 100
D. 110