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Unit 4 - Practice Quiz

CSE211

1 What does the acronym HDL stand for in the context of digital systems?

A. Hardware Description Language
B. High-level Design Language
C. Hardware Design Logic
D. Hybrid Digital Logic

2 Which of the following statements best describes the primary difference between an HDL (like Verilog) and a software programming language (like C)?

A. HDLs are compiled into binary executables, while software languages are synthesized.
B. HDLs inherently support concurrency and time, while software languages are primarily sequential.
C. Software languages run faster than HDLs.
D. HDLs are object-oriented, while software languages are procedural.

3 In the standard HDL-based design flow, what is the process of converting an RTL description into a gate-level netlist called?

A. Simulation
B. Synthesis
C. Floorplanning
D. Verification

4 Which of the following is not a typical step in the HDL design flow?

A. Functional Simulation
B. Logic Synthesis
C. Operating System Compilation
D. Place and Route

5 What is the purpose of a testbench in Verilog?

A. To physically connect the chip to a circuit board.
B. To generate stimulus and verify the functionality of the design module.
C. To synthesize the design into gates.
D. To optimize the power consumption of the circuit.

6 In Verilog, which operator is used for non-blocking assignment?

A. =
B. :=
C. <=
D. ==

7 Which Verilog keyword is used to declare a signal that retains its value until a new value is assigned (often used inside always blocks)?

A. wire
B. net
C. reg
D. logic

8 In Register Transfer Language (RTL), what does the notation imply?

A. The contents of register R2 are compared to R1.
B. The contents of register R1 are transferred to register R2.
C. The contents of register R2 are transferred to register R1.
D. Registers R1 and R2 are swapped.

9 How is a conditional control function represented in Register Transfer Language?

A.
B.
C.
D.

10 In the statement , what does the comma indicate?

A. The operations are performed sequentially.
B. The operations are performed simultaneously.
C. The first operation has higher priority.
D. The statement is syntactically incorrect.

11 Which digital component is primarily used to construct a common bus system using multiplexers?

A. Decoder
B. Encoder
C. Multiplexer
D. Flip-flop

12 When using three-state buffers to construct a bus, what is the output state when the control input is disabled (logic 0)?

A. Logic 0
B. Logic 1
C. High Impedance (Hi-Z)
D. Unknown (X)

13 Which RTL statement represents a Memory Read operation where is memory and is the Address Register?

A.
B.
C.
D.

14 Which RTL statement represents a Memory Write operation?

A.
B.
C.
D.

15 Which of the following is NOT a category of micro-operations?

A. Register transfer micro-operations
B. Arithmetic micro-operations
C. Logic micro-operations
D. Network micro-operations

16 The arithmetic micro-operation represents which operation?

A. Addition
B. Subtraction ()
C. Increment
D. Decrement

17 Which logic gate is used to implement the Selective Complement micro-operation?

A. AND
B. OR
C. XOR
D. NAND

18 Which logic micro-operation is used to clear specific bits in a register to 0?

A. Selective Set (OR)
B. Selective Clear (AND with complement)
C. Selective Complement (XOR)
D. Mask (AND)

19 In an Arithmetic Shift Right (ashr), what happens to the most significant bit (sign bit)?

A. It is filled with 0.
B. It is filled with 1.
C. It remains unchanged (sign extension).
D. It takes the value of the least significant bit.

20 What is the result of a Logical Shift Left on the binary number $1011$?

A. 0101
B. 1101
C. 0110
D. 0111

21 A Circular Shift (or Rotate) operation behaves as follows:

A. Bits shifted out at one end are lost.
B. Bits shifted out at one end are inserted at the opposite end.
C. Zeros are always inserted.
D. Ones are always inserted.

22 In a 4-bit binary adder, how is the output Carry () calculated for the -th stage using Propagate () and Generate ()?

A.
B.
C.
D.

23 The overflow condition for signed 2's complement addition of two numbers is detected by:

A.
B.
C.
D.

24 In a hardware multiplication algorithm for unsigned integers, what two main operations are repeated?

A. Add and Subtract
B. Shift and Add
C. Increment and Compare
D. Load and Store

25 What is the primary advantage of Booth's Multiplication Algorithm?

A. It is faster for all inputs.
B. It handles signed binary numbers in 2's complement directly.
C. It requires fewer gates than an array multiplier.
D. It eliminates the need for a clock.

26 In Booth's algorithm, if the multiplier bit pair is 10, what operation is performed?

A. Add Multiplicand to Partial Product
B. Subtract Multiplicand from Partial Product
C. Arithmetic Shift Right only
D. Logical Shift Left

27 In Booth's algorithm, if the multiplier bit pair is 01, what operation is performed?

A. Add Multiplicand to Partial Product
B. Subtract Multiplicand from Partial Product
C. Shift only
D. Complement Multiplicand

28 In Booth's algorithm, if the multiplier bit pair is 00 or 11, what operation is performed?

A. Add Multiplicand
B. Subtract Multiplicand
C. Arithmetic Shift Right only
D. Set Partial Product to 0

29 Which Verilog syntax correctly defines a module with inputs A, B and output Y?

A. module test(input A, B, output Y); ... endmodule
B. define module test(A, B, Y); ... end
C. module test { A, B, Y }; ... endmodule
D. function test(A, B) return Y;

30 What is a Netlist?

A. A list of internet servers.
B. A textual description of circuit connectivity (gates and wires).
C. A high-level C++ code.
D. A timing diagram.

31 Which HDL modeling style describes the system by how data flows through the logic (using Boolean equations)?

A. Behavioral Modeling
B. Dataflow Modeling
C. Structural Modeling
D. Switch-level Modeling

32 Which HDL modeling style connects pre-defined modules (instantiation) to build a larger system?

A. Behavioral Modeling
B. Dataflow Modeling
C. Structural Modeling
D. Algorithmic Modeling

33 In Verilog, the always @(posedge clk) block is used to model:

A. Combinational logic only
B. Sequential logic (Synchronous)
C. Constant values
D. Asynchronous logic only

34 In RTL, a register assumed to hold the address for memory operations is typically denoted as:

A. DR (Data Register)
B. AR (Address Register)
C. AC (Accumulator)
D. PC (Program Counter)

35 What is the result of the logic micro-operation ?

A. A is set to all 1s.
B. A is cleared to all 0s.
C. A remains unchanged.
D. A is complemented.

36 The operation is called:

A. Shift
B. Load
C. Increment
D. Clear

37 In a bus system using a Decoder, the output of the decoder is used to:

A. Carry data.
B. Select the source register.
C. Store data.
D. Perform arithmetic.

38 Which Verilog symbol represents the bitwise AND operator?

A. &&
B. &
C. AND
D. |

39 Which Verilog symbol represents the Concatenation operator?

A. &
B. ||
C. {}
D. []

40 In RTL, the notation refers to:

A. The address of the memory.
B. The memory word located at the address specified by AR.
C. The multiplication of M and AR.
D. An array index.

41 A Universal Shift Register typically has the capability to:

A. Only shift left.
B. Only shift right.
C. Shift left, shift right, and parallel load.
D. Only parallel load.

42 When implementing a Bus transfer using Multiplexers, if there are 4 registers of 16 bits each, what size multiplexers are needed?

A. One MUX
B. Sixteen MUXs
C. Four MUXs
D. One MUX

43 What is the hardware equivalent of the RTL statement ?

A. Connect output of R2 to input of R1 with a wire/bus and trigger R1's load.
B. Connect output of R1 to input of R2.
C. Use an AND gate between R1 and R2.
D. Use a subtractor.

44 In Verilog, #10 indicates:

A. A hexadecimal number 10.
B. A binary number 10.
C. A time delay of 10 units.
D. A loop that runs 10 times.

45 Which of the following best describes Functional Verification?

A. Checking if the chip overheats.
B. Checking if the logic behaves according to the specification without considering timing delays.
C. Checking signal propagation delays.
D. Checking the physical layout rules.

46 What is the result of the Selective Set operation on data $1010$ with mask $1100$?

A. 1000
B. 0010
C. 1110
D. 0110

47 The RTL statement represents:

A. Clearing R1.
B. Complementing R1 (1's complement) when P is active.
C. Negating R1 (2's complement).
D. Setting R1 to High Impedance.

48 In a 4-bit Binary Adder-Subtractor circuit, the mode input controls the operation. If , the circuit performs:

A. Addition
B. Subtraction
C. Multiplication
D. Division

49 Which standard body manages the Verilog language definition?

A. ISO
B. ANSI
C. IEEE
D. W3C

50 What constitutes a Micro-operation?

A. A complex software function.
B. An elementary operation performed on information stored in one or more registers during one clock pulse.
C. A complete instruction cycle.
D. A high-level programming command.