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Unit 5 - Practice Quiz

CSE211

1 Which principle allows the Memory Hierarchy to function effectively by assuming that data accessed recently will likely be accessed again soon?

A. Principle of Relativity
B. Locality of Reference
C. Direct Memory Access
D. Cycle Stealing

2 In the context of RAM, which of the following statements distinguishes SRAM from DRAM?

A. SRAM requires periodic refreshing, while DRAM does not.
B. SRAM is slower than DRAM.
C. SRAM uses flip-flops for storage, while DRAM uses capacitors.
D. DRAM is more expensive per bit than SRAM.

3 Arrange the following memory types in descending order of speed (Fastest to Slowest):

A. Cache, Registers, Main Memory, Magnetic Disk
B. Registers, Cache, Main Memory, Magnetic Disk
C. Main Memory, Cache, Registers, Magnetic Disk
D. Registers, Main Memory, Cache, Magnetic Disk

4 If the CPU finds the word it is looking for in the cache memory, it is called a:

A. Page Fault
B. Cache Miss
C. Cache Hit
D. Segment Fault

5 Calculate the average memory access time if the Cache access time is , Main memory access time is , and the Hit ratio is $0.9$.

A.
B.
C.
D.

6 In which mapping technique is a block of main memory mapped to a specific fixed line in the cache?

A. Associative Mapping
B. Set-Associative Mapping
C. Direct Mapping
D. Virtual Mapping

7 Which hardware component is primarily required for Associative Mapping to search all cache lines simultaneously?

A. Multiplexer
B. Content Addressable Memory (CAM)
C. Counter
D. Decoder

8 In a -way set-associative cache, each set contains how many cache lines?

A. $1$
B.
C. Total Cache Lines /
D. Dependent on block size

9 What is the primary disadvantage of the Write-through policy in cache memory?

A. It causes data inconsistency.
B. It generates high memory traffic because every write goes to main memory.
C. It is complex to implement.
D. It requires a Dirty Bit.

10 In the Write-back policy, when is the data updated in the main memory?

A. Immediately upon every write request.
B. Only when the cache block is evicted/replaced.
C. At fixed time intervals.
D. When the CPU is idle.

11 Which bit is used in the Write-back method to indicate that a cache block has been modified?

A. Valid bit
B. Dirty bit
C. Present bit
D. Modify bit

12 Which cache replacement algorithm replaces the block that has not been used for the longest period of time?

A. FIFO (First In First Out)
B. LFU (Least Frequently Used)
C. LRU (Least Recently Used)
D. Random

13 Virtual Memory allows the execution of programs that are:

A. Smaller than the main memory.
B. Larger than the physical main memory.
C. Stored only in ROM.
D. Written in Assembly language.

14 In Virtual Memory, the addresses used by the programmer are called ____ addresses, and the addresses in the physical memory are called ____ addresses.

A. Physical, Logical
B. Logical, Physical
C. Binary, Decimal
D. Relative, Absolute

15 The fixed-size blocks of virtual memory are called ____, and the fixed-size blocks of physical memory are called ____.

A. Frames, Pages
B. Pages, Frames
C. Segments, Blocks
D. Sectors, Tracks

16 What is a Page Fault?

A. An error in the page table code.
B. Accessing a page that is not currently in main memory.
C. Writing to a read-only page.
D. A hardware failure in RAM.

17 What is the function of the TLB (Translation Lookaside Buffer)?

A. To store the entire Page Table.
B. To cache recent Virtual-to-Physical address translations.
C. To perform arithmetic operations.
D. To manage hard disk sectors.

18 Which problem occurs when memory is divided into variable-length partitions (Segmentation), leading to unused gaps between allocated memory blocks?

A. Internal Fragmentation
B. External Fragmentation
C. Page Fault
D. Thrashing

19 Which access method is used by Magnetic Tapes?

A. Random Access
B. Direct Access
C. Sequential Access
D. Associative Access

20 What is Seek Time in a magnetic disk?

A. Time to transfer data to the bus.
B. Time for the sector to rotate under the head.
C. Time to move the read/write head to the specified track.
D. Total time to read a file.

21 According to Flynn's Taxonomy, a traditional Uniprocessor (von Neumann architecture) is classified as:

A. SISD (Single Instruction, Single Data)
B. SIMD (Single Instruction, Multiple Data)
C. MISD (Multiple Instruction, Single Data)
D. MIMD (Multiple Instruction, Multiple Data)

22 Which classification of parallel computers is best suited for Vector Processing / Array Processors?

A. SISD
B. SIMD
C. MISD
D. MIMD

23 In Pipelining, what is the theoretical speedup achievable with a -stage pipeline assuming no stalls?

A.
B.
C.
D.

24 What is a Structural Hazard in pipelining?

A. Dependency between data of two instructions.
B. Branching instructions changing the flow.
C. Hardware resource conflict (e.g., two stages needing memory at the same time).
D. A voltage drop in the CPU.

25 A situation where an instruction depends on the result of a previous instruction that has not yet completed is called:

A. Structural Hazard
B. Data Hazard
C. Control Hazard
D. Branch Hazard

26 What technique is commonly used to minimize the performance penalty of Control Hazards (Branching)?

A. Operand Forwarding
B. Branch Prediction
C. Memory Interleaving
D. Cache Coherence

27 Which of the following defines Throughput in a pipelined processor?

A. The time to process a single instruction.
B. The number of instructions completed per unit time.
C. The number of pipeline stages.
D. The clock frequency.

28 In a Tightly Coupled Multiprocessor system:

A. Processors do not share memory.
B. Processors share a global main memory.
C. Communication is done via message passing over LAN.
D. Each processor has its own OS copy.

29 Which interconnection structure uses a set of crosspoints where a switch determines the path between a processor and a memory module?

A. Time-Shared Common Bus
B. Crossbar Switch
C. Hypercube
D. Ring Network

30 In a Time-Shared Common Bus system, how is conflict resolved when multiple processors want to access the bus?

A. Data is merged.
B. Arbitration logic (Arbiter).
C. The bus shuts down.
D. Random selection.

31 The Omega Network is an example of which type of interconnection structure?

A. Static Topology
B. Multistage Switching Network
C. Crossbar Switch
D. Shared Bus

32 What is the Cache Coherence problem in multiprocessors?

A. The cache is too small.
B. Multiple caches may hold different values for the same memory block.
C. The cache is slower than main memory.
D. The processor cannot read the cache.

33 Which protocol is commonly used to maintain Cache Coherence in bus-based multiprocessors?

A. Snoopy Protocol
B. Sliding Window Protocol
C. Handshaking Protocol
D. Interrupt Protocol

34 In a Hypercube interconnection network, a system with nodes has a node degree (connections per node) of:

A.
B.
C.
D.

35 What distinguishes NUMA (Non-Uniform Memory Access) from UMA (Uniform Memory Access)?

A. NUMA has no shared memory.
B. In NUMA, memory access time depends on the memory location relative to the processor.
C. NUMA is strictly for single processors.
D. UMA allows faster access to remote memory.

36 What is Memory Interleaving?

A. Mixing ROM and RAM chips.
B. Dividing memory into modules that can be accessed in parallel.
C. Storing data in non-volatile memory.
D. Using virtual memory for cache.

37 If a computer has a 32-bit address bus, what is the maximum addressable memory space?

A. $1$ GB
B. $2$ GB
C. $4$ GB
D. $8$ GB

38 What is the role of a Multiport Memory?

A. To allow only one processor to access memory at a time.
B. To allow multiple processors to access separate internal memory modules simultaneously.
C. To replace cache memory.
D. To store only instructions.

39 Which pipelining hazard is resolved using Pipeline Interlocking (Stalling)?

A. It is used to clear the cache.
B. It halts the pipeline for one or more cycles to resolve a Data Hazard.
C. It increases the clock speed.
D. It is used for branch prediction.

40 In the context of Cache Mapping, what is the Tag?

A. The data stored in the cache.
B. A unique identifier stored with the block to determine which main memory block is currently in the line.
C. The index of the cache set.
D. The offset within the block.

41 Loosely Coupled Multiprocessors typically use which scheme for communication?

A. Shared Memory variables
B. Message Passing
C. Common Register File
D. Direct wire connection

42 Which of the following is an advantage of Associative Mapping over Direct Mapping?

A. Simpler hardware.
B. Lower cost.
C. Higher hit ratio due to flexibility in block placement.
D. No need for replacement algorithms.

43 What occurs when the system spends more time swapping pages in and out than executing instructions?

A. Deadlock
B. Thrashing
C. Paging
D. Interleaving

44 In a Vector Processor, instructions operate on:

A. Single scalar values.
B. One-dimensional arrays of data (vectors).
C. Only boolean values.
D. Only integer values.

45 Which equation represents the speedup factor of a pipeline, where is time without pipeline and is time with pipeline?

A.
B.
C.
D.

46 What is the primary function of the Bootstrap Loader?

A. To load the operating system from disk to main memory upon startup.
B. To clean the cache.
C. To manage virtual memory pages.
D. To synchronize processors.

47 In a Directory-based cache coherence protocol, where is the information about the status of memory blocks stored?

A. In each processor's cache controller only.
B. In a centralized or distributed directory.
C. In the hard disk.
D. In the instruction register.

48 Which write policy is easiest to implement if the cache uses a parity bit for error detection?

A. Write-back
B. Write-through
C. Write-once
D. Write-allocation

49 Assuming a cache size of 64KB and a block size of 16 bytes, how many lines (blocks) are in the cache?

A. $1024$
B. $2048$
C. $4096$
D. $8192$

50 What is the specific benefit of Pipelining in processors?

A. It reduces the latency of a single instruction.
B. It increases the overall throughput of instruction execution.
C. It eliminates branch hazards.
D. It increases the clock cycle time.