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Unit 3 - Practice Quiz

CSE211

1 Which of the following best defines a peripheral device in computer organization?

A. The central processing unit and the main memory
B. An internal cache memory used for high-speed storage
C. Input or output devices attached to the computer
D. The system bus connecting the CPU to memory

2 Which alphanumeric code is most commonly used in peripheral devices to transfer characters?

A. BCD
B. ASCII
C. Gray Code
D. Excess-3 Code

3 What is the primary function of an Input-Output Interface?

A. To perform arithmetic calculations on data
B. To resolve differences between the CPU and peripheral devices
C. To store data permanently
D. To increase the clock speed of the CPU

4 In Isolated I/O configuration, how are I/O addresses treated compared to memory addresses?

A. They share the same address space
B. I/O addresses are distinct and have their own read/write control lines
C. I/O devices are accessed using memory instructions like MOV
D. The CPU cannot access I/O devices directly

5 What is a characteristic of Memory-Mapped I/O?

A. It requires distinct input and output instructions
B. It uses a separate address bus for I/O
C. I/O devices and memory share the same address space
D. It is faster than isolated I/O because it bypasses memory

6 In asynchronous data transfer, which control signal indicates that data is placed on the bus by the source unit?

A. Acknowledge
B. Strobe
C. Interrupt
D. Hold

7 What is the major disadvantage of the Strobe Control method of asynchronous data transfer?

A. It is too slow
B. It requires too many wires
C. The source unit has no way of knowing if the destination unit received the data
D. It cannot transfer 16-bit data

8 Which mechanism solves the timing problem of the Strobe method by ensuring the destination has received the data?

A. Handshaking
B. Polling
C. Cycle Stealing
D. Multiplexing

9 In Programmed I/O, what is the state of the CPU while waiting for the I/O device to become ready?

A. It executes other programs
B. It enters a low-power sleep mode
C. It stays in a loop checking the status flag (busy-waiting)
D. It grants control to the DMA controller

10 Which mode of transfer allows the I/O device to alert the CPU when it is ready, eliminating busy-waiting?

A. Programmed I/O
B. Interrupt-initiated I/O
C. Synchronous Transfer
D. Serial Transfer

11 Which method is used to establish priority by connecting all interrupt sources in a serial connection?

A. Polling
B. Daisy Chaining
C. Parallel Priority
D. Cyclic Redundancy Check

12 In a Daisy Chaining priority interrupt system, what happens if a device receives a 'Propose Priority' signal but does not have an interrupt pending?

A. It blocks the signal
B. It passes the signal to the next device in the chain
C. It generates a trap
D. It sends an interrupt acknowledge to the CPU

13 What is Polling in the context of priority interrupts?

A. A hardware mechanism using priority encoders
B. A software technique where the CPU checks each device sequentially
C. A method of direct memory access
D. A way to reset all I/O devices

14 What is the Vector Address in a vectored interrupt system?

A. The memory address where the data is stored
B. The physical address of the I/O device
C. The address of the interrupt service routine
D. The address of the last executed instruction

15 Which hardware component is commonly used to implement a Parallel Priority Interrupt system?

A. Shift Register
B. Priority Encoder
C. Counter
D. Multiplexer

16 What does the CPU do immediately after acknowledging an interrupt?

A. It shuts down
B. It clears the main memory
C. It pushes the Program Counter (PC) and Status Register to the stack
D. It resets the I/O interface

17 What does DMA stand for?

A. Digital Memory Allocation
B. Direct Memory Access
C. Dynamic Memory Architecture
D. Data Management Area

18 What is the main advantage of DMA transfer?

A. It simplifies the CPU architecture
B. It allows high-speed data transfer between memory and I/O without CPU intervention
C. It eliminates the need for an address bus
D. It reduces the size of main memory

19 Which signal does the DMA controller send to the CPU to ask for control of the system bus?

A. Bus Grant (BG)
B. Bus Request (BR)
C. Interrupt Request (IRQ)
D. Chip Select (CS)

20 What is Cycle Stealing in DMA?

A. The DMA controller steals data bits from the CPU
B. The CPU takes cycles away from the DMA controller
C. The DMA controller transfers one word at a time by taking control of the bus for one memory cycle
D. The operating system steals cycles from the user program

21 Which DMA transfer mode locks the bus until the entire block of data is transferred?

A. Cycle Stealing
B. Burst Transfer (Block Transfer)
C. Transparent Mode
D. Demand Transfer

22 Which register in the DMA controller keeps track of the number of words to be transferred?

A. Address Register
B. Control Register
C. Word Count Register
D. Status Register

23 Who initializes the DMA controller registers before a transfer begins?

A. The I/O Device
B. The CPU
C. The Main Memory
D. The DMA Controller itself

24 What is an Input-Output Processor (IOP)?

A. A software routine for I/O
B. A processor with direct memory access capability that communicates with I/O devices
C. A standard CPU used for arithmetic
D. A type of memory

25 How does the CPU communicate with an IOP?

A. By sharing the accumulator
B. By leaving instructions in a shared memory area
C. By serial cable
D. The CPU cannot communicate with an IOP

26 Which type of I/O Channel is designed to handle multiple slow-speed devices simultaneously?

A. Selector Channel
B. Multiplexer Channel
C. Burst Channel
D. Isolated Channel

27 A Selector Channel is best suited for:

A. Connecting a single high-speed device (like a disk)
B. Connecting many slow devices (like printers/terminals)
C. Performing arithmetic operations
D. Wireless communication

28 What does UART stand for?

A. Unified Asynchronous Receiver Technology
B. Universal Asynchronous Receiver/Transmitter
C. Universal Array of Receiver Timing
D. Unique Address Receiver Transfer

29 In UART communication, how is data transmitted?

A. Parallelly, 8 bits at a time
B. Serially, bit by bit
C. Using DMA blocks
D. Via the address bus

30 What is the purpose of the Start Bit in UART transmission?

A. To indicate the end of data
B. To check for errors
C. To signal the receiver that a character is starting
D. To set the clock speed

31 What is Baud Rate?

A. The total memory size
B. The rate at which data is transferred (bits per second)
C. The speed of the CPU
D. The voltage level of the signal

32 What is the function of the Parity Bit in serial transfer?

A. To stop the transmission
B. To detect errors in transmission
C. To increase transmission speed
D. To encrypt the data

33 If a UART configuration is '8N1', what does it mean?

A. 8 bits data, No parity, 1 Stop bit
B. 8 bits data, New parity, 1 Start bit
C. 8 bits data, No start bit, 1 parity
D. 8 interrupts, No DMA, 1 CPU

34 Which error occurs in UART if the stop bit is not detected at the expected time?

A. Parity Error
B. Framing Error
C. Overrun Error
D. Burst Error

35 Which interface command is used to check if a peripheral is ready to send data?

A. Control command
B. Status command
C. Data output command
D. Data input command

36 In the context of Priority Interrupts, what is the purpose of the Mask Register?

A. To store the data temporarily
B. To selectively enable or disable specific interrupts
C. To count the number of interrupts
D. To generate the vector address

37 The transmission of data where each character is preceded by a start bit and followed by a stop bit is called:

A. Synchronous transmission
B. Asynchronous transmission
C. Parallel transmission
D. Isochronous transmission

38 Which signal indicates that the DMA transfer is complete?

A. Bus Request
B. Bus Grant
C. DMA Acknowledge
D. Interrupt (End of Process)

39 In a Memory-Mapped I/O system, what instruction would be used to read data from an input device?

A. IN PortAddress
B. LOAD Register, MemoryAddress
C. READ Port
D. INPUT DeviceID

40 Which buffer is commonly used in UART interfaces to temporarily hold data during speed mismatches?

A. LIFO
B. FIFO
C. Stack
D. Heap

41 What is the result of in a parallel priority interrupt system if there are interrupt sources?

A. The number of priority encoders needed
B. The size of the mask register
C. The number of priority levels is not , but usually equal to
D. The clock speed required

42 Which I/O technique allows the CPU to execute instructions out of order relative to I/O operations effectively?

A. Programmed I/O
B. DMA
C. Polling
D. Manual Switch Control

43 In the standard I/O Interface block diagram, the Control line is used to:

A. Carry data bits
B. Carry the address of the device
C. Specify the command (Read, Write, Status)
D. Supply power

44 What is an Overrun Error in serial communication?

A. The baud rates do not match
B. The CPU reads data too fast
C. New data arrives before the old data in the receive buffer has been read
D. The start bit is missing

45 Which of the following equations represents the calculation for the time to transfer a block in Cycle Stealing mode? ( = total time, = number of words, = memory cycle time, = CPU processing time between steals)

A.
B.
C.
D.

46 Which component in an I/O interface decodes the device address sent by the CPU?

A. Address Decoder
B. Data Register
C. Status Register
D. Control Logic

47 In a 2-wire handshaking protocol, if the Source initiates the transfer, the sequence starts with:

A. Source activating Data Valid
B. Destination activating Data Accepted
C. Source activating Request
D. Destination activating Ready for Data

48 Unlike a standard CPU, an IOP typically does NOT have:

A. Arithmetic Logic Unit (ALU) for complex floating-point math
B. DMA capability
C. Ability to execute instructions
D. Registers

49 The Interrupt Acknowledge (INTACK) signal is sent by:

A. The Peripheral to the CPU
B. The CPU to the Peripheral
C. The Memory to the DMA
D. The DMA to the Memory

50 Which of the following is an example of a Parallel Interface?

A. USB
B. SATA
C. IEEE 1284 (Centronics)
D. I2C