Unit4 - Subjective Questions

The evolution of HDLs can be categorized as follows:

• Early Beginnings: In the late 1960s and 1970s, as designs moved from MSI to LSI, schematic diagrams became too complex. Languages like ISP (Instruction Set Processor) were created to describe functionality, but they could not directly simulate hardware.
• Emergence of PLDs: In the late 1970s, Programmable Logic Devices (PLDs) emerged, leading to languages like ABEL (Advanced Boolean Expression Language) and CUPL for programming equations into logic chips.
• The VHDL Era: In the early 1980s, the US Department of Defense (DoD) initiated the VHSIC (Very High Speed Integrated Circuit) program, leading to the creation of VHDL (VHSIC Hardware Description Language). It became an IEEE standard (1076) in 1987.
• The Verilog Era: Around 1984, Gateway Design Automation created Verilog. It was simpler and modeled after C programming. It became an IEEE standard (1364) in 1995.
• Modern Era: Today, SystemVerilog and SystemC have evolved to handle complex SoC (System on Chip) designs, integrating verification and high-level behavioral modeling.

A typical HDL-based design flow involves the following steps:

1. Design Entry: The functionality of the system is described using an HDL (Verilog/VHDL) or via schematic capture.
2. Functional Simulation: The design is verified logically to ensure it behaves as expected before any timing implementation. Testbenches are used here.
3. Synthesis: The HDL code is translated by a synthesis tool into a netlist (a gate-level representation) mapped to a specific technology library (ASIC or FPGA).
4. Placement and Routing (P&R): The gates and connections defined in the netlist are physically placed on the chip area and wired together.
5. Timing Simulation/Verification: Post-synthesis simulation is performed to check for timing violations (setup/hold time) introduced by physical delays.
6. Device Programming/Fabrication: The final bitstream is generated to program an FPGA, or masks are created for ASIC fabrication.

1. Concurrency vs. Sequential Execution:

• SPLs (e.g., C, Python): Execute instructions sequentially (one after another).
• HDLs (e.g., Verilog): Model hardware where multiple blocks and signals operate concurrently (in parallel). A change in a clock signal can trigger hundreds of flip-flops simultaneously.

2. Timing Concept:

• SPLs: Time is a measure of CPU cycles required to run the code. Explicit timing control is difficult.
• HDLs: Time is a central concept. Constructs like #10 (delay) or @(posedge clk) allow precise modeling of propagation delays and clock edges.

3. Structure:

• SPLs: Use variables, functions, and classes mapped to memory addresses.
• HDLs: Use wires, registers, and modules mapped to physical logic gates and flip-flops.

4. Purpose:

• SPLs: To create algorithms for a processor to execute.
• HDLs: To describe the structure and behavior of the processor/circuit itself.

A Verilog module is the basic building block of a design. It starts with the keyword module and ends with endmodule.

Basic Syntax Structure:

1. Module Declaration: Name and port list (inputs/outputs).
2. Port Declarations: Defining which ports are input and which are output.
3. Data Type Declarations: wire or reg.
4. Module Body: Contains assignments, gate instantiations, or always blocks.

Example: Half Adder

verilog
module HalfAdder (A, B, Sum, Carry);
// Port Declarations
input A, B;
output Sum, Carry;

// Logic Description (Dataflow style)
assign Sum = A ^ B;    // XOR operation
assign Carry = A & B;  // AND operation

endmodule

Definition: Register Transfer Language (RTL) is a symbolic notation used to describe the micro-operations aimed at transferring data between registers. It represents the internal organization of a digital computer.

Basic Notation:

• Registers: Denoted by capital letters (e.g., , , ).
• Transfer: The operator denotes a transfer of information.
  • Example: implies the content of is copied into .
• Bit Selection: Parentheses are used to denote part of a register.
  • Example: refers to the lower 8 bits of .

Control Functions:

• Transfer usually occurs only under specific control conditions.
• Notation:
• Here, is a control signal (boolean variable). The transfer occurs only if and the clock edge arrives. This translates to hardware as: is loaded with when enable is high.

A common bus system allows multiple registers to share a single data path. For four registers () of 4 bits each, we need a 4-bit wide bus.

Construction:

1. Multiplexers Required: Since the bus must carry 4 bits, we need four Multiplexers (MUX 0 to MUX 3).
2. Inputs:
   • MUX 0 receives the 0th bit of registers A, B, C, and D.
   • MUX 1 receives the 1st bit of registers A, B, C, and D.
   • ...and so on.
3. Selection Lines: Two selection lines () are connected to all multiplexers.

Working:

• The selection lines decide which register places its data on the bus.
• If : Input 0 of all MUXes is selected (Register A is on the bus).
• If : Input 1 is selected (Register B is on the bus).
• The output of the MUXes constitutes the common bus lines, which can then be connected to the inputs of all registers.

A three-state (tri-state) buffer is a gate that has three output states: Logic 0, Logic 1, and High Impedance (High-Z).

Construction of the Bus:

1. Instead of multiplexers, the output of each register bit is connected to a three-state buffer.
2. The outputs of all buffers corresponding to bit of all registers are connected together to form Bus Line .
3. Control: A Decoder is used to control the 'Enable' pins of the buffers.
   • A decoder takes selection inputs .
   • The decoder outputs enable only one set of buffers (one register) at a time.

Working:

• If Register A is selected, its buffers are enabled (low impedance). Its data flows to the bus.
• All other registers' buffers are disabled (High-Z). They act as open circuits, electrically disconnecting those registers from the bus.
• This prevents short circuits and signal contention.

Memory Transfer involves moving data between memory words and processor registers. We usually denote the Memory unit as and the Address Register as .

1. Read Operation:

• This transfers a word from memory to a register (e.g., Data Register ).
• The address of the word must be in the .
• RTL: Read:
• Meaning: Content of the memory word addressed by is transferred to .

2. Write Operation:

• This transfers the content of a register (e.g., ) into a memory word.
• RTL: Write:
• Meaning: Content of is transferred to the memory word addressed by .

A micro-operation is an elementary operation performed on the information stored in one or more registers during one clock pulse.

1. Register Transfer Micro-operations:
   • Transfer binary information from one register to another. Does not change the information content.
   • Example: .
2. Arithmetic Micro-operations:
   • Perform arithmetic on data stored in registers.
   • Examples: Addition, Subtraction, Increment, Decrement, Complement.
3. Logic Micro-operations:
   • Perform bit manipulation operations on non-numeric data.
   • Examples: XOR, AND, OR, NOT (Bitwise).
4. Shift Micro-operations:
   • Shift the data in registers laterally.
   • Examples: Shift Left, Shift Right, Rotate.

The digital circuit that performs both addition and subtraction is called a Binary Adder-Subtractor. It utilizes Full Adders (FA) and XOR gates.

Components:

• 4 Full Adders.
• 4 XOR gates.
• One mode control input .

Construction:

• Input () connects directly to the FA inputs.
• Input () connects to one input of the XOR gates. The other input of the XOR gates is connected to Mode .
• The carry input () of the least significant FA is connected to .

Operation:

1. Addition ():
   • .
   • . The XOR gates pass unchanged.
   • The circuit performs .
2. Subtraction ():
   • .
   • (1's complement of B).
   • The circuit performs . This is effectively (2's complement of ), which is .

Logic micro-operations specify binary operations for strings of bits stored in registers. They consider each bit separately.

Applications:

1. Selective-Set (using OR):

   • Forces bits to 1 where the control bit is 1.
   • Example: , . .
   • Result . (Bits were set where B was 1).

2. Selective-Clear (using AND with Complement):

   • Forces bits to 0 where the control bit is 1.
   • Operation: .
   • Example: , . .

3. Selective-Complement (using XOR):

   • Inverts bits where the control bit is 1.
   • Operation: .
   • Example: , . Result $0110$.

Shift micro-operations are used for serial transfer of data or arithmetic scaling.

1. Logical Shift:

   • Transfers 0 through the serial input.
   • shl: Shift left (inserts 0 at LSB).
   • shr: Shift right (inserts 0 at MSB).
   • Used for unsigned numbers.

2. Circular Shift (Rotate):

   • Circulates the bits of the register around the two ends without loss of information.
   • cil: Circular left (MSB moves to LSB).
   • cir: Circular right (LSB moves to MSB).

3. Arithmetic Shift:

   • Shifts a signed binary number left or right.
   • ashl: Arithmetic shift left (Same as logical shift left, usually; overflow may occur).
   • ashr: Arithmetic shift right. Preserves the sign bit. The sign bit (MSB) is shifted to the right, but a copy of the sign bit is re-inserted into the MSB position.

An arithmetic shift right () must preserve the sign bit () for signed 2's complement numbers. This is effectively division by 2.

Implementation Logic:

1. Let the register be .
2. During the shift:
   • (Sign bit moves to position ).
   • (For all other bits).
3. Critical Step: .
   • The sign bit remains unchanged in the most significant position, effectively "extending" the sign.

Example:

• Input: 1010 (-6 in decimal).
• Shift Right: 1101 (-3 in decimal).
• The '1' at MSB was copied into the next slot, and also kept at the MSB.

A Universal Shift Register is a versatile register capable of performing multiple operations: Hold, Shift Right, Shift Left, and Parallel Load.

Components:

• 4 D Flip-Flops.
• 4 Multiplexers.
• Selection inputs .

Connections:

• The output of each MUX connects to the D input of a Flip-Flop.
• Mode Selection ():
  • 00 (No Change): MUX input 0 is selected. Output of flip-flop feeds back to itself.
  • 01 (Shift Right): MUX input 1 is selected. Serial Input Right enters MSB; goes to , etc.
  • 10 (Shift Left): MUX input 2 is selected. Serial Input Left enters LSB; goes to , etc.
  • 11 (Parallel Load): MUX input 3 is selected. External parallel data inputs () are loaded into the flip-flops.

An ALSU is a digital circuit that performs arithmetic (add, sub), logic (and, or, xor), and shift operations. It is the core of the CPU.

One Stage Diagram (One bit slice):

• Inputs: Two operand bits , and a Carry Input .
• Components:
  1. Arithmetic Circuit: Typically a Full Adder with input logic for (to handle subtraction).
  2. Logic Circuit: Gates for AND, OR, XOR, NOT.
  3. Multiplexer: A large MUX (e.g., or ) selects the result from the arithmetic circuit or the specific logic gate based on Selection lines.
  4. Shift Logic: The output of the MUX might pass through shift logic (shifters) before reaching the final output .

(Note: In a subjective exam, you would draw a MUX collecting outputs from a Full Adder and Logic Gates, controlled by selection lines).

In signed-magnitude representation, the MSB is the sign, and the rest is magnitude. Operations are more complex than 2's complement.

Algorithm Logic:
Let quantities be and , with signs .

1. Check Operation:
   • If Add (): If signs are identical (), add magnitudes. Sign of result = .
   • If signs are different (), compare magnitudes.
2. Magnitude Comparison (when signs differ in Add, or same in Sub):
   • Subtract smaller magnitude from larger ( or ).
   • Sign of result = Sign of the larger magnitude.
3. Subtraction ():
   • Invert sign of B (), then proceed as Addition.

Hardware Requirements:

• Registers A and B.
• Parallel Adder.
• Comparator (to check ).
• Mode Control logic (XORing signs).

This describes the standard "Shift and Add" method.

Registers:

• A: Accumulator (Initially 0).
• Q: Multiplier.
• B: Multiplicand.
• SC: Sequence Counter (set to number of bits ).

Flowchart Steps:

1. Check LSB of Multiplier ().
2. If : Add Multiplicand to Accumulator (). Then Shift.
3. If : No addition. Just Shift.
4. Shift: Shift Right the combined register pair and ().
   • Carry moves into MSB of .
   • LSB of moves into MSB of .
   • LSB of is discarded.
5. Decrement Counter ().
6. Loop: If $SC
   eq 0SC = 0A-Q$.

Concept: Booth's algorithm is a multiplication algorithm for signed binary numbers in 2's complement notation. It treats strings of 1s in the multiplier as a single block to reduce operations.

Why Preferred?

• Standard "Shift and Add" does not work directly for negative numbers in 2's complement (requires correction steps).
• Booth's algorithm handles positive and negative numbers uniformly without pre-processing.
• It can be faster if the multiplier has large blocks of consecutive 1s (e.g., 011110) by replacing additions with a subtraction and an addition.

Logic:
It inspects two bits: (current LSB) and (previous LSB, initially 0).

1. 00 or 11: String of 0s or 1s. Arithmetic Shift Right (ASHR) only.
2. 10: End of a string of 1s. Subtract Multiplicand from A (), then ASHR.
3. 01: Beginning of a string of 1s. Add Multiplicand to A (), then ASHR.

Setup:

• Multiplicand () = = $1011$ (4-bit 2's comp).
• (for subtraction) = $0101$.
• Multiplier () = $3$ = $0011$.
• Accumulator () = $0000$.
• = $0$.
• Sequence Counter () = $4$.

Steps:

Result: The result is in and : $11110001$.
Checking in 2's complement: Invert and add 1 . Correct.