Unit 6: Introduction to GPU Architecture - Practice Quiz

1 What does the acronym GPU stand for?

2 Which parallel computing platform and programming model was developed by Nvidia?

3 In Nvidia GPU terminology, the basic parallel execution units are called:

4 GPUs are especially well suited for which type of processing?

5 A supercomputer is a computer that primarily offers very high:

6 The performance of supercomputers is commonly measured in:

7 Which term describes a supercomputer capable of at least floating-point operations per second?

8 Most modern supercomputers achieve their power by using:

9 What is the basic unit of information in quantum computing called?

10 Unlike a classical bit, a qubit can exist in a combination of both states at once due to:

11 The quantum phenomenon where two qubits become correlated so the state of one affects the other is called:

12 A classical bit can hold how many possible values at any given time?

13 Which trend refers to placing multiple processing cores on a single chip?

14 Moore's Law originally predicted that the number of transistors on a chip would:

15 Which term describes processors that combine CPU and GPU on the same die?

16 Which open-standard instruction set architecture is widely used in next-generation designs?

17 Executing more than one instruction per clock cycle is a feature of which processor type?

18 The term microarchitecture refers to:

19 Which microarchitectural technique overlaps the execution stages of multiple instructions?

20 Which company designs the ARM-based A-series and M-series chips used in its smartphones, tablets, and desktops?

21 In NVIDIA's CUDA programming model, a group of threads that execute the same instruction in lockstep on an SM is called a:

22 NVIDIA introduced dedicated units for accelerating matrix multiply-accumulate operations used in deep learning. These are known as:

23 If an NVIDIA GPU has 80 Streaming Multiprocessors and each SM can hold up to 2048 resident threads, the maximum number of concurrently resident threads is:

24 The performance of supercomputers in the TOP500 list is primarily measured using which benchmark?

25 A supercomputer achieves floating-point operations per second. This performance level is classified as:

26 Modern supercomputers largely achieve high performance through which architectural approach?

27 A quantum system with qubits can represent how many basis states simultaneously in superposition?

28 Which property allows two qubits to be correlated such that the state of one instantly influences the measured state of the other?

29 The loss of quantum information due to unwanted interaction with the environment is called:

30 A single qubit state must satisfy which normalization condition?

31 The trend of building processors from multiple smaller dies connected within a single package is known as:

32 The end of Dennard scaling primarily led to which shift in processor design?

33 High Bandwidth Memory (HBM) achieves greater bandwidth than traditional DDR mainly by:

34 Domain-specific accelerators (like TPUs) outperform general-purpose CPUs for AI workloads mainly because they:

35 The RISC-V instruction set architecture is notable for being:

36 Neuromorphic processors are designed to mimic which system to achieve energy-efficient computation?

37 In a superscalar processor, out-of-order execution improves performance primarily by:

38 A pipeline with 5 stages ideally increases throughput compared to a non-pipelined design by a factor of up to:

39 Branch prediction is used in modern microarchitectures mainly to:

40 Simultaneous Multithreading (SMT), such as Intel's Hyper-Threading, improves utilization by:

41 In NVIDIA's SIMT execution model, a warp of 32 threads encounters a data-dependent branch where 20 threads take the if path and 12 take the else path. Assuming no independent thread scheduling (pre-Volta), what is the effective SIMD utilization during the divergent region?

42 NVIDIA Tensor Cores accelerate matrix multiply-accumulate operations. If a Tensor Core computes a by matrix multiply-accumulate () per clock, how many fused multiply-add (FMA) operations does one such operation represent?

43 A supercomputer achieves a peak (theoretical) performance of PFLOPS but a sustained LINPACK () of PFLOPS. What does the ratio primarily quantify, and what is its approximate value here?

44 Amdahl's Law limits the speedup of a parallel program. If of a workload is parallelizable and a supercomputer offers effectively unlimited processors, what is the maximum theoretical speedup?

45 A quantum register of qubits can represent a superposition of how many basis states simultaneously, and how does this scale compared to classical bits?

46 Which statement best characterizes why quantum decoherence is a fundamental engineering challenge, rather than merely a noise problem solvable by shielding?

47 Grover's search algorithm provides a quadratic speedup for unstructured search over items. For a database of entries, approximately how many oracle queries does Grover's algorithm need versus a classical average-case search?

48 As Dennard scaling ended, power density stopped decreasing with transistor size, leading to the 'dark silicon' phenomenon. What does dark silicon most directly refer to?

49 Chiplet-based designs (e.g., disaggregating a monolithic die into multiple smaller dies on an interposer) primarily improve manufacturing economics because of which relationship?

50 High Bandwidth Memory (HBM) achieves very high bandwidth despite modest clock rates primarily through which architectural approach?

51 In a heterogeneous big.LITTLE / performance-efficiency core design, the scheduler migrates a latency-sensitive foreground thread from an efficiency core to a performance core. What is the primary architectural challenge that makes such migration non-trivial?

52 RISC-V's use of modular, optional ISA extensions (e.g., M, A, F, D, V) contrasts with fixed ISAs. From an architectural standpoint, what is the main trade-off this modularity introduces?

53 A superscalar out-of-order processor uses register renaming. What fundamental hazard does register renaming eliminate, and what hazard does it NOT eliminate?

54 Consider a 5-stage pipeline with a branch resolved in the execute (3rd) stage and no branch prediction (predict-not-taken with squash on taken). If of instructions are branches and of those are taken, causing a 2-cycle penalty each, what is the approximate CPI contribution from branch stalls?

55 Simultaneous Multithreading (SMT, e.g., Hyper-Threading) improves throughput by filling idle issue slots from multiple threads. Under what condition does SMT provide the LEAST benefit?

56 Apple's M-series and A-series SoCs employ a Unified Memory Architecture (UMA). Compared to a traditional discrete-GPU system with separate VRAM, what is the principal architectural advantage of UMA for GPU-CPU workloads?

57 Modern mobile SoCs integrate a dedicated NPU (Neural Processing Unit) alongside CPU and GPU. Why is a specialized NPU more energy-efficient than running the same neural inference on the CPU or GPU?

58 On an NVIDIA GPU, memory coalescing combines the global-memory accesses of a warp into fewer transactions. If all 32 threads of a warp access consecutive 4-byte words within a single aligned 128-byte segment, how many memory transactions are ideally required?

59 A supercomputer is rated at PFLOPS and consumes MW of power. What is its energy efficiency in GFLOPS/watt, and why is this metric increasingly the binding constraint for exascale systems?

60 Near-memory and in-memory computing (e.g., processing-in-memory, PIM) architectures aim to overcome which specific bottleneck of the classical von Neumann model?