Unit6 - Subjective Questions

Serial-In Serial-Out (SISO) Shift Register:

In a SISO shift register, data enters the register serially (one bit at a time) and exits serially.

Operation:

1. It consists of flip-flops (usually D-type) connected in a cascade arrangement.
2. The output of one flip-flop is connected to the input of the next.
3. All flip-flops are synchronized by a common clock pulse.
4. For an -bit register, it takes clock pulses to load the data completely and clock pulses to shift the data out.

Example (4-bit SISO):

• Initially cleared: $0000$
• Input Data: $1011$
• Clock 1: $1$ enters FF0 Output: $1000$
• Clock 2: Next bit $0$ enters, $1$ shifts to FF1 Output: $0100$
• Clock 3: Next bit $1$ enters Output: $1010$
• Clock 4: Next bit $1$ enters Output: $1101$

Data is available at the final output serially.

Serial-In Parallel-Out (SIPO) Shift Register:

Working:

1. Data is entered serially into the register, bit by bit, synchronized with the clock.
2. Once the data is loaded, the outputs of all flip-flops () are available simultaneously (in parallel).
3. For a 4-bit register, 4 clock pulses are required to load the data. Once loaded, the data is immediately available on parallel lines without further clock pulses.

Diagram Description:

• Input enters .
• , , etc.
• Outputs are taken from directly.

Applications:

• Serial to Parallel conversion: Used in communication systems where data arrives on a single wire but the processor requires parallel data (e.g., UART).
• Driving parallel displays from a serial data source.

Parallel-In Serial-Out (PISO) Shift Register:

This register allows parallel loading of data bits and shifts them out serially.

Circuit Logic:
It utilizes a combinational circuit (usually AND-OR gates) at the input of each flip-flop to select between the 'Parallel Load' input and the 'Serial Shift' input. This is controlled by a Shift/Load () control line.

Modes of Operation:

1. Parallel Load Mode ():
   • The gates enable the parallel input data lines () to enter the flip-flops directly.
   • The data is loaded asynchronously or synchronously (depending on design) in 1 clock pulse.
2. Serial Shift Mode ():
   • The gates disable parallel inputs and enable the output of the previous flip-flop to connect to the next input ().
   • On subsequent clock pulses, data shifts out serially from the last flip-flop.

Application: Used for converting parallel data buses to serial communication lines.

Parallel-In Parallel-Out (PIPO) Register:

Operation:

1. Inputs ( to ) are connected directly to the inputs of the respective flip-flops.
2. Outputs ( to ) are taken directly from the flip-flops.
3. Upon the application of a single clock pulse, the binary data available at the inputs is loaded into the flip-flops and appears immediately at the outputs.

Speed:

• It is the fastest register because it requires only 1 clock pulse to load the data and 0 clock pulses (instantaneous) for the output to be available.
• No shifting is involved.

Application:

• Used as a temporary storage or buffer memory in digital systems.

Comparison between Asynchronous and Synchronous Counters:

3-bit Asynchronous (Ripple) Up Counter:

Components: Three JK Flip-Flops (FF0, FF1, FF2) operating in Toggle Mode ().

Construction:

1. Clock: The external clock is applied only to the clock input of the first flip-flop (FF0).
2. Cascading: The output of FF0 acts as the clock input for FF1. The output of FF1 acts as the clock input for FF2.
3. Triggering: Negative edge-triggered flip-flops are typically used for Up-counting when connecting to Clock.

Operation:

• Initially .
• Pulse 1: FF0 toggles on the falling edge. goes . FF1 sees a rising edge (no change).
• Pulse 2: FF0 toggles . This falling edge triggers FF1. FF1 toggles . Count: $010$.
• Pulse 4: FF0 toggles , triggers FF1 (), which triggers FF2 (). Count: $100$.

This ripples through until count $111$, after which it resets to $000$.

Propagation Delay in Asynchronous Counters:

1. Ripple Effect: In an asynchronous counter, the clock pulse is applied only to the LSB flip-flop. The change in state of the LSB triggers the next bit, which triggers the next, and so on.
2. Accumulation: Each flip-flop has an internal propagation delay (). For an -bit counter, the total time required for the MSB to settle after a clock pulse is .

Frequency Limit:
To ensure valid data is read, the clock period () must be greater than the total settling time.

As the number of bits () increases, the maximum operating frequency decreases significantly compared to synchronous counters.

Mod-10 Asynchronous Counter Design:

A Mod-10 counter counts from $0$ ($0000$) to $9$ ($1001$) and resets to $0$ on the 10th pulse.

Requirements:

• 4 Flip-Flops are needed ().
• A standard 4-bit ripple up counter counts . We must truncate the sequence at 10 ().

Reset Logic:

1. The counter behaves normally from $0000$ to $1001$.
2. On the 10th pulse, the counter temporarily goes to state $1010$ ().
3. This state must immediately trigger a CLR (Clear) or RESET operation on all flip-flops.
4. Logic Gate: A NAND gate is used.
   • Inputs to NAND: and (the high bits of 10).
   • Output of NAND is connected to the active-low inputs of all flip-flops.

Operation:
When state $1010$ is reached, NAND output goes LOW, resetting the counter to $0000$ almost instantly (glitch state).

Asynchronous Down Counter:

An asynchronous counter can be configured to count down (e.g., ) by changing how the clock of the subsequent flip-flops is triggered.

Configuration Methods (assuming Negative Edge Triggered FFs):

1. Method A (Using ): Connect the inverted output () of the previous flip-flop to the clock input of the next flip-flop.
2. Method B (Using Positive Edge FFs): If using positive edge-triggered FFs, connecting to the next clock creates a down counter.

3-Bit Down Counter Operation (Method A):

• FFs are in Toggle mode ().
• Clock: Applied to FF0.
• FF1 Clock: Connected to .
• FF2 Clock: Connected to .

Logic: When changes from , changes (falling edge). This triggers the next bit. This logic results in the sequence decrementing.

Synchronous Counter:
In a synchronous counter, all flip-flops are triggered by the same clock signal simultaneously. The transition of states is controlled by the logic levels at the (or ) inputs.

Design Steps for 3-bit Up Counter (using T-FFs):

1. Determine Number of FFs: 3 bits require 3 Flip-Flops ().
2. State Diagram: Sequence .
3. Excitation Table (T-FF): (No Change) if ; (Toggle) if $Q{next} \
   eq Q{curr}$.
4. State Table: List Current State, Next State, and required T inputs.
   • Example: transition . toggles (), toggles (), toggles ().
5. K-Map Simplification:
   • (Always toggles).
   • (Toggles when is 1).
   • (Toggles when both and are 1).
6. Logic Diagram: Implement using AND gates for the T inputs.

Mod-6 Synchronous Counter Design:

This counter counts $0, 1, 2, 3, 4, 5$ and resets to $0$.

Design Logic:

1. Flip-Flops: Need 3 FFs (). States: $000$ to $101$.
2. Invalid States: $110$ (6) and $111$ (7). These are 'Don't Cares' in K-Maps, or must reset to 0.
3. Using T-Flip Flops (Example Logic):
   • Drive the logic inputs () based on K-maps derived from the state transition table ().

Logic Equations (Simplified):

• (if counting all states, but for Mod-6 logic changes slightly to prevent state 6).
• Typically designed using a reset logic or specific K-map minimization where state $101$ transitions to $000$.
• Next State Logic for : It toggles unless the state is $101$.

Unlike asynchronous Mod-N which uses a Clear signal on a partial state, Synchronous Mod-N uses logic gates at the J/K/T inputs to force the transition from directly to $0$ on the next clock pulse, avoiding glitches.

Synchronous Up/Down Counter:

This circuit can count both upwards and downwards based on a control input signal, usually labeled M (Mode) or Up/.

Logic:

1. Up Counting: Requires the flip-flop to toggle when all previous bits are High ($1$).
2. Down Counting: Requires the flip-flop to toggle when all previous bits are Low ($0$).

Control Circuit:

• We use a combinational logic block for the T or JK inputs.
• Let for Up and for Down.
• For the -th flip-flop :
  
• This looks like an OR of two AND gates (one handling the Up condition, one handling the Down condition).

Operation:

• If , the 'Up' AND gates are enabled, 'Down' gates disabled. The circuit acts as an Up counter.
• If , the 'Down' AND gates are enabled (using outputs). The circuit acts as a Down counter.

Ring Counter:

A Ring Counter is a specific application of a Serial-In Serial-Out (SISO) shift register where the output of the last flip-flop is connected back to the input of the first flip-flop.

Construction:

• Logic: .
• Initialization: It requires a specific initial state, typically a "One-hot" state (e.g., $1000$ for a 4-bit counter), set via PRESET/CLEAR inputs.

Operation (4-bit):

• Start: $1000$ (Active bit at MSB).
• Clock 1: The '1' shifts right. State: $0100$.
• Clock 2: Shifts right. State: $0010$.
• Clock 3: Shifts right. State: $0001$.
• Clock 4: The '1' from wraps around to . State: $1000$.

Characteristics:

• Modulo- for flip-flops.
• Used for stepper motor control or sequential timing signals.

Johnson Ring Counter (Twisted Ring Counter):

It is a variation of the Ring Counter where the inverted output of the last flip-flop is connected to the input of the first flip-flop.

Difference from Standard Ring Counter:

1. Feedback:
   • Ring:
   • Johnson: (Twisted feedback)
2. Number of States (Modulus):
   • Ring: states (for flip-flops).
   • Johnson: states.
3. Sequence (4-bit example):
   • Starts $0000$.
   • Fills with 1s: .
   • Fills with 0s: .
4. Hardware: Johnson counters provide more states for the same number of flip-flops compared to a standard Ring counter.

4-bit Johnson Counter State Table:

Assuming initialization at $0000$ and feedback (if shifting left) or (if shifting right). Let's assume right shift ( is LSB, is MSB, gets is wrong, standard is ).

Let's assume shift Right: . Feedback: .

Modulus:
The pattern repeats after 8 clock pulses.
Modulus = .

Comparison: Ring Counter vs. Johnson Counter

3-bit Ripple Down Counter Waveforms:

Setup:

• 3 Flip-flops ().
• Start Count: $111$ (7).
• Trigger: Falling edge of Clock for . Falling edge of (or rising of ) triggers , etc.

Waveform Description:

1. Clock: Regular square wave.
2. (LSB): Toggles on every negative edge of the Clock. Frequency = .
3. (Bit 1): Toggles when changes from (if using to drive clock in specific config) or standard ripple logic. For a Down counter, bits toggle when previous bit goes (Positive transition) if using negative edge FFs connected to .
   • Visual: toggles half as often as .
4. (MSB): Toggles when triggers it. Frequency = .

Sequence:
Input pulses produce binary sequence: $111, 110, 101, 100, 011, 010, 001, 000$.

Frequency Division using Counters:

Counters inherently act as frequency dividers because the output of each flip-flop toggles at a lower rate than its input clock.

Principle:

• In a binary ripple counter, the output of the first flip-flop () divides the clock frequency by 2 ().
• The second flip-flop () divides by 2, resulting in .
• The -th flip-flop output provides a frequency of .

Mod-N Division:
To divide a frequency by a specific integer (not just powers of 2), a Mod-N counter is used.

• Example: To get a 1 MHz signal from a 10 MHz clock, a Mod-10 (Decade) counter is used. The output of the MSB (or the carry out) will pulse once for every 10 input pulses.

Application: Digital watches (dividing crystal frequency to 1 Hz), Baud rate generators.

Lock-out in Counters:

Lock-out occurs when a counter enters an unused or invalid state (a state not in its desired sequence) due to noise or power-up conditions, and logically cannot return to the valid sequence loop. The counter remains "locked" in these invalid states.

Example in Ring Counter:

• Valid states for 3-bit: $100, 010, 001$.
• If noise sets it to $101$, typical ring logic might shift it to , never returning to the valid "one-hot" sequence.

Resolution (Self-Starting Logic):
To solve this, additional logic gates are added to the feedback loop to ensure that if the counter falls into an invalid state, it will eventually be forced back into the valid sequence.

• For a Ring Counter, logic is added such that if $000$ (or other invalid patterns) are detected, a '1' is injected to restart the cycle.

Applications of Sequential Circuits:

1. Frequency Division: Counters are used to reduce high-frequency clock signals to lower frequencies for digital timing (e.g., in digital clocks).
2. Data Storage and Transfer: Registers are used within CPUs to hold data temporarily (Buffer Registers) and to transfer data between different parts of a system (SISO, PIPO operations).
3. Serial-to-Parallel / Parallel-to-Serial Conversion: Shift registers are essential in communication interfaces (like USB, UART) to convert data formats for transmission.
4. Time Measurement: Counters are used in digital voltmeters, frequency counters, and timers to measure time intervals or count events.
5. Sequence Generation: Ring and Johnson counters are used to generate control signals or specific timing sequences for stepper motors and traffic light controllers.